JPS6486262A - Data transferring device - Google Patents

Data transferring device

Info

Publication number
JPS6486262A
JPS6486262A JP24446687A JP24446687A JPS6486262A JP S6486262 A JPS6486262 A JP S6486262A JP 24446687 A JP24446687 A JP 24446687A JP 24446687 A JP24446687 A JP 24446687A JP S6486262 A JPS6486262 A JP S6486262A
Authority
JP
Japan
Prior art keywords
transferring
address
circuit
area
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24446687A
Other languages
Japanese (ja)
Inventor
Keizou Naraba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24446687A priority Critical patent/JPS6486262A/en
Publication of JPS6486262A publication Critical patent/JPS6486262A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To improve transferring efficiency by reading the area contents of a memory specified with a converting address different from an address at the time of previous data transferring and setting the area specifying data to a transferring register. CONSTITUTION:At a DMA (direct memory access) controller 21 is provided with a DMA control part 2, a transferring address value register 3, and a transferring size value register 4, and address registers 22 and 23 to indicate area addresses in which a transferring address value and a transferring size value are stored respectively and a transfer completing detecting circuit 24 and an address converting circuit 25 are connected to the control part 2. Thereafter, at the time of starting a DMA, the address values in the registers 22 and 23 are sent to the circuit 25 through the circuit 24, the area data specified by the converting addresses are read and set to registers 23 and 24.
JP24446687A 1987-09-29 1987-09-29 Data transferring device Pending JPS6486262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24446687A JPS6486262A (en) 1987-09-29 1987-09-29 Data transferring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24446687A JPS6486262A (en) 1987-09-29 1987-09-29 Data transferring device

Publications (1)

Publication Number Publication Date
JPS6486262A true JPS6486262A (en) 1989-03-30

Family

ID=17119066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24446687A Pending JPS6486262A (en) 1987-09-29 1987-09-29 Data transferring device

Country Status (1)

Country Link
JP (1) JPS6486262A (en)

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