JPS5682959A - Memory information transfer system - Google Patents

Memory information transfer system

Info

Publication number
JPS5682959A
JPS5682959A JP15948579A JP15948579A JPS5682959A JP S5682959 A JPS5682959 A JP S5682959A JP 15948579 A JP15948579 A JP 15948579A JP 15948579 A JP15948579 A JP 15948579A JP S5682959 A JPS5682959 A JP S5682959A
Authority
JP
Japan
Prior art keywords
memory
memory control
controller
external
connection pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15948579A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Fumitaka Sato
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15948579A priority Critical patent/JPS5682959A/en
Publication of JPS5682959A publication Critical patent/JPS5682959A/en
Pending legal-status Critical Current

Links

Landscapes

  • Microcomputers (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To enable to decrease the number of external connection pins greatly by sending memory control information out without providing external connection pins characteristic to an information output for memory control.
CONSTITUTION: Arithmetic controller 101, made into one chip of a very large scale integrated semiconductor, is controlled by external control memory part 102 stored with a microprogram. At main bus 103, output data, memory data, etc., of memory part 102 arrive in time-division mode. Then when controller 101 is supplied with a microinstruction, one of external signal groups is inputted to controller 101 via bus 103 together with the microinstruction and during the transfer of memory addresses, memory control information is sent onto bus 103 together with memory addresses. Therefore, the number of external connection pins can be decreased greatly by sending memory control information out without providing external pins characteristic to information outputs for memory control.
COPYRIGHT: (C)1981,JPO&Japio
JP15948579A 1979-12-08 1979-12-08 Memory information transfer system Pending JPS5682959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15948579A JPS5682959A (en) 1979-12-08 1979-12-08 Memory information transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15948579A JPS5682959A (en) 1979-12-08 1979-12-08 Memory information transfer system

Publications (1)

Publication Number Publication Date
JPS5682959A true JPS5682959A (en) 1981-07-07

Family

ID=15694793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15948579A Pending JPS5682959A (en) 1979-12-08 1979-12-08 Memory information transfer system

Country Status (1)

Country Link
JP (1) JPS5682959A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255455A (en) * 1985-05-07 1986-11-13 Mitsubishi Electric Corp Data memory controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52122438A (en) * 1976-04-07 1977-10-14 Sanyo Electric Co Ltd Write-in and read-out system
JPS53132231A (en) * 1977-04-25 1978-11-17 Hitachi Ltd Control unit for data write-in

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52122438A (en) * 1976-04-07 1977-10-14 Sanyo Electric Co Ltd Write-in and read-out system
JPS53132231A (en) * 1977-04-25 1978-11-17 Hitachi Ltd Control unit for data write-in

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255455A (en) * 1985-05-07 1986-11-13 Mitsubishi Electric Corp Data memory controller

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