JPS57174753A - Information processor - Google Patents

Information processor

Info

Publication number
JPS57174753A
JPS57174753A JP6089181A JP6089181A JPS57174753A JP S57174753 A JPS57174753 A JP S57174753A JP 6089181 A JP6089181 A JP 6089181A JP 6089181 A JP6089181 A JP 6089181A JP S57174753 A JPS57174753 A JP S57174753A
Authority
JP
Japan
Prior art keywords
data
address
access
memory
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6089181A
Other languages
Japanese (ja)
Inventor
Yoshikuni Satou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6089181A priority Critical patent/JPS57174753A/en
Publication of JPS57174753A publication Critical patent/JPS57174753A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize the transfer of data at a high speed with the overlapping of both cycles of the memory and the data, by leaving an address to an external address holding circuit while a processor itself is giving an access to a memory device and delivering successively the addresses to which an access will be given in the future to select the memory.
CONSTITUTION: An address is supplied to an address holding circuit 204 by the bus group selection signal and an output signal 228. Thus the address is delivered to an address line 213 to reach a memory device 202. An access is given to a selected memory address, and the data is delivered to a data line 214. The data is then fed to a data bus 212 of the processor side through a data buffer 205 to be fetched into a microprocessor 201. The data is read out of a memory device 203 by an access signal 227 to the device 203 and a signal 225 indicating the direction of data during the time T7WT9. Then the data is transferred to the microprocessor 201 through a data line 216, a data buffer 207 and the bus 212 respectively.
COPYRIGHT: (C)1982,JPO&Japio
JP6089181A 1981-04-22 1981-04-22 Information processor Pending JPS57174753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6089181A JPS57174753A (en) 1981-04-22 1981-04-22 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6089181A JPS57174753A (en) 1981-04-22 1981-04-22 Information processor

Publications (1)

Publication Number Publication Date
JPS57174753A true JPS57174753A (en) 1982-10-27

Family

ID=13155428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6089181A Pending JPS57174753A (en) 1981-04-22 1981-04-22 Information processor

Country Status (1)

Country Link
JP (1) JPS57174753A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154018A (en) * 1985-12-26 1987-07-09 Fujitsu Ltd Semiconductor disk device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154018A (en) * 1985-12-26 1987-07-09 Fujitsu Ltd Semiconductor disk device

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