JPS5571338A - Hdlc receiving system - Google Patents

Hdlc receiving system

Info

Publication number
JPS5571338A
JPS5571338A JP14484778A JP14484778A JPS5571338A JP S5571338 A JPS5571338 A JP S5571338A JP 14484778 A JP14484778 A JP 14484778A JP 14484778 A JP14484778 A JP 14484778A JP S5571338 A JPS5571338 A JP S5571338A
Authority
JP
Japan
Prior art keywords
memory
data
receiving
control
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14484778A
Other languages
Japanese (ja)
Other versions
JPS619782B2 (en
Inventor
Akimasa Yatsuhoshi
Kiyoji Yamauchi
Shiyunichi Iisaku
Takashi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14484778A priority Critical patent/JPS5571338A/en
Publication of JPS5571338A publication Critical patent/JPS5571338A/en
Publication of JPS619782B2 publication Critical patent/JPS619782B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To make it possible to reduce the load of processor unit PU and constitute PU with a simple general LSI, etc., by terminating data transfer operations by the end timing read out from a control buffer memory. CONSTITUTION:Receiving HDLC (high-level data link control) circuit 4 converts coming serial data to parallel data and stores this data in data buffer memory 6. Data of the last packet and the end timing are stored in memory 6 and control buffer memory 7 respectively, and simultaneously, receiving completion is reported to PU1. Then, PU1 starts operations of receiving DMAC (direct memory access control) circuit 3, and data stored in memory 6 is transferred to memory 2 by DMA (direct memory access). At the last data transfer from memory 6 to memory 2, control information is read out from memory 7, and then, operations of receiving DMAC circuit 3 are stopped.
JP14484778A 1978-11-22 1978-11-22 Hdlc receiving system Granted JPS5571338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14484778A JPS5571338A (en) 1978-11-22 1978-11-22 Hdlc receiving system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14484778A JPS5571338A (en) 1978-11-22 1978-11-22 Hdlc receiving system

Publications (2)

Publication Number Publication Date
JPS5571338A true JPS5571338A (en) 1980-05-29
JPS619782B2 JPS619782B2 (en) 1986-03-26

Family

ID=15371796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14484778A Granted JPS5571338A (en) 1978-11-22 1978-11-22 Hdlc receiving system

Country Status (1)

Country Link
JP (1) JPS5571338A (en)

Also Published As

Publication number Publication date
JPS619782B2 (en) 1986-03-26

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