JPS56166563A - Error control system - Google Patents

Error control system

Info

Publication number
JPS56166563A
JPS56166563A JP7009880A JP7009880A JPS56166563A JP S56166563 A JPS56166563 A JP S56166563A JP 7009880 A JP7009880 A JP 7009880A JP 7009880 A JP7009880 A JP 7009880A JP S56166563 A JPS56166563 A JP S56166563A
Authority
JP
Japan
Prior art keywords
data
bit
storage device
address information
data processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7009880A
Other languages
Japanese (ja)
Inventor
Yutaka Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7009880A priority Critical patent/JPS56166563A/en
Publication of JPS56166563A publication Critical patent/JPS56166563A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To enable to confirm the erroneous or normal control only with one data transmission and to speed up the processing, by effectively using the data bus, in a system where a storage device and a data processor are connected with a data bus. CONSTITUTION:A data processor 1 and a storage device 2 are provided with additional bit registers 14, 24, and the additional bits are fed from the data processor 1 to the storage device 2 with the address information, and the data and the additional bits are written in a memory 20 according to the address information. In case of normal transfer mode, the data is stored in the memory 20 based on the address information with the correction bit produced from a one bit correction control section 25. Thus, the data processor 1 reads out these two types of data and compares the additional bits with the correction bit, allowing to confirm whether the one bit correction control section 25 is normal or not.
JP7009880A 1980-05-28 1980-05-28 Error control system Pending JPS56166563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7009880A JPS56166563A (en) 1980-05-28 1980-05-28 Error control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7009880A JPS56166563A (en) 1980-05-28 1980-05-28 Error control system

Publications (1)

Publication Number Publication Date
JPS56166563A true JPS56166563A (en) 1981-12-21

Family

ID=13421707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7009880A Pending JPS56166563A (en) 1980-05-28 1980-05-28 Error control system

Country Status (1)

Country Link
JP (1) JPS56166563A (en)

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