JPS57157333A - Memory address control system - Google Patents

Memory address control system

Info

Publication number
JPS57157333A
JPS57157333A JP4380781A JP4380781A JPS57157333A JP S57157333 A JPS57157333 A JP S57157333A JP 4380781 A JP4380781 A JP 4380781A JP 4380781 A JP4380781 A JP 4380781A JP S57157333 A JPS57157333 A JP S57157333A
Authority
JP
Japan
Prior art keywords
line
registers
address
energized
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4380781A
Other languages
Japanese (ja)
Inventor
Takashi Nakamura
Masao Gohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4380781A priority Critical patent/JPS57157333A/en
Publication of JPS57157333A publication Critical patent/JPS57157333A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To increase the efficiency of data transfer and buffer management, by shortening the bit length of an address specifying a buffer block, in the buffer management of a processor. CONSTITUTION:When a memory address by an address designation line 33 does not designate the 1st and 2nd registers 23-25, a comparison circuit 26 energizes a control line 51 and sets the address on the line 33 to registers 20,21 and 22. The contents of the registers 20 and 23 are compared 52, and when they are coincident, a control line 44 is energized, the least significant bit of the register 21 is discriminated with a selection circuit 53 and a control line 46 or 47 is energized. Thus, an AND gate 28 or 29 is opened, the contents of the register 24 or 25 are outputted on a line 42 and given to a memory control circuit 9. If dissident, a control line 43 is energized and the contents of the registers 20 and 22 are transmitted to the memory control circuit 9 as they are with lines 34, 42 and 36 as a memory address.
JP4380781A 1981-03-25 1981-03-25 Memory address control system Pending JPS57157333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4380781A JPS57157333A (en) 1981-03-25 1981-03-25 Memory address control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4380781A JPS57157333A (en) 1981-03-25 1981-03-25 Memory address control system

Publications (1)

Publication Number Publication Date
JPS57157333A true JPS57157333A (en) 1982-09-28

Family

ID=12674009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4380781A Pending JPS57157333A (en) 1981-03-25 1981-03-25 Memory address control system

Country Status (1)

Country Link
JP (1) JPS57157333A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6399952U (en) * 1986-12-18 1988-06-29

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6399952U (en) * 1986-12-18 1988-06-29

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