JPH056893B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] When an instruction processing unit (IPU) makes a fetch request to a storage control unit (SCU) having a buffer storage device (BS), an instruction fetch request (IFRQ) and an operand fetch request are sent. Tutsi Request (OPRQ)
In a storage access method in which both of
When the instruction processing unit (IPU) is executed, an interlock is applied to the instruction processing unit (IPU) to suppress operations in the instruction processing unit (IPU). This is what made it possible.

[Industrial application field]

The present invention provides a storage control unit (SCU) having a buffer storage unit (BS) from an instruction processing unit (IPU).
The present invention relates to an instruction prefetch method in a memory access method in which both an instruction fetch request and an operand fetch request are performed using the same path when a fetch request is made to a memory access method.

BACKGROUND ART With the recent remarkable spread of computer systems, the amount of data processed by these computer systems has increased, and there is a trend that demands for improved processing capabilities of these computer systems are becoming higher and higher.

1 to improve the processing power of computer systems
One well-known method is the so-called pipeline method, in which multiple instructions are simultaneously executed in each processing unit.However, in a pipeline-based computer system, each instruction input to the pipeline is interrupted. It is an essential condition that pre-fetched instructions always exist in the instruction buffer provided in the instruction processing unit (IPU) so that there are no errors.

FIG. 3 is a diagram showing the prefetch state of the instruction buffer, where IFRQ indicates an instruction fetch request in the instruction processing unit (IPU) 1, and OPRQ
(A) and (B) show operand fetch requests in the instruction processing unit (IPU) 1.

As shown in this figure, in a pipeline control computer system, the instruction buffer always contains
It is required that some instructions be prefetched.

[Conventional technology]

In small and medium-sized computer systems, from the viewpoint of cost performance, the fetch request route (specifically, the fetch address sending route) is
It may be configured to be shared by both instruction fetch requests (IFRQ) and operand fetch requests (OPRQ).

In this case, in general, a control method is used that prioritizes operand fetches over instruction fetches so as not to interfere with instruction execution. It functions so that it is suppressed.

A memory access operation in a conventional system having the above characteristics will be explained with reference to FIGS. 4 and 5.

FIG. 4 is a diagram illustrating a storage access method in a conventional pipeline control computer system, and FIG. 5 is a time chart showing the operation of the conventional storage access method.

First, when a certain instruction is sent to the instruction execution unit 12 of the instruction processing unit (IPU) 1 having a pipeline configuration, an address for an operand fetch request (OPRQ) A is sent at timing T0, and the address for the operand fetch request (OPRQ) A is sent at timing T1. When it is detected that the operand does not exist in the buffer storage (BS) 21 of the storage control unit (SCU) 2 (this is called BS missing),
The storage control unit (SCU) 2 interlocks the instruction processing unit (IPU) 1 at timing T1 when receiving the operand requested by the instruction processing unit (IPU) 1. The operation of the instruction execution unit is stopped.

Thereafter, as is clear from the time chart in FIG. 5, the address bus remains in the state as soon as the next operand fetch request (OPRQ) B is sent.

[Problem that the invention seeks to solve]

Therefore, if the address transfer path is shared by operand fetch requests (OPRQ) and instruction fetch requests (IFRQ),
In the conventional system, when instructions with consecutive operand accesses continue, the address bus is occupied by the operand addresses and instruction prefetching is not possible, as shown in FIG. 6, which explains the problems of the conventional technique. There is a problem in that the instruction buffer (not shown) in the instruction control unit 11 becomes 'empty', making it impossible to perform efficient pipeline processing.

In view of the above-mentioned conventional drawbacks, the present invention provides that when an instruction processing unit (IPU) issues an operand fetch request (OPRQ) and the above-mentioned BS missing occurs, the instruction processing unit (IPU) The purpose of this invention is to provide a method for reducing the frequency at which instruction prefetching becomes impossible, focusing on the fact that an interlock is applied to the instruction and execution of the instruction is inhibited.

[Means for solving problems]

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the present invention, a storage control unit (SCU) 2
has a buffer storage device (BS) 21, and receives both an instruction fetch request (IFRQ) and an operand fetch request (OPRQ) from the instruction processing unit (IPU) 1 to the storage control unit (SCU) 2.
If an operand fetch request (OPRQ) is sent from the instruction processing unit (IPU) 1 for an operand that uses the same path and does not exist in the buffer storage device (BS) 21, the storage control Device (SCU) 2 is instruction processing unit (IPU) 1
In a memory access method having a function of interlocking the instruction processing unit (IPU) 1 and inhibiting the operation of the instruction processing unit (IPU) 1, the operand is transferred from the main memory to the buffer storage (BS) 21 during the interlock. As means for opening the fetch request path until the data is transferred, a circuit is provided which outputs an AND signal 2a-1 of the signal that accepted the operand fetch request and the missing signal that caused the interlock. The instruction is fetched even during the interlock by using the AND signal 2a-1 from the circuit.

[Effect]

That is, according to the present invention, an instruction processing unit (IPU)
When making a fetch request to a storage control unit (SCU) that has a buffer storage device (BS),
In a memory access method that uses the same path for both an instruction fetch request (IFRQ) and an operand fetch request (OPRQ), for an operand that does not exist in the buffer storage device (BS),
When an operand fetch request (OPRQ) is issued from the instruction processing unit (IPU) mentioned above, an interlock is applied to the instruction processing unit (IPU) to inhibit operations in the instruction processing unit (IPU). while,
Since the fetch path is opened to enable fetching of instructions during interlock, it has the effect of reducing the frequency at which the instruction buffer in the instruction execution section of the instruction processing unit (IPU) becomes ``empty''.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
The above-mentioned FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart showing the instruction prefetch operation when the present invention is implemented. The instruction prefetch control signal 2a during interlock is a necessary means to implement the present invention.

Even if the present invention is implemented, the normal instruction fetch request (IFRQ) operation and operand fetch request (OPRQ) operation are the same as before, so they will be omitted here, and the focus will be on the instruction prefetch operation according to the present invention. explain.

First, at timing T0, the instruction processing unit (IPU) 1 issues a message to the storage control unit (SCU) 2.
Executes operand fetch request (OPRQ) A and stores the buffer storage (BS) of storage control unit (SCU) 2.
21, the operand reception timing T1
When BS missing is detected, the control unit 22 is accessed.

The control unit 22 of the storage control unit (SCU) 2 interlocks the instruction execution unit 12 of the instruction processing unit (IPU) 1 at the timing of T1 to inhibit execution of the instruction.

At this time, in the present invention, the control unit 22 of the storage control unit (SCU) 2 is an instruction processing unit (IPU).
In contrast to 1, the cause of the above interlock is BS and missing in operand fetch processing, and thereafter the requested operand is the instruction processing unit (IPU).
1, the AND signal 2a of the signal that accepted the operand fetch request and the missing signal that caused the interlock.
An AND signal 2a-1 is sent from a circuit that outputs -1.

The instruction processing unit (IPU) 1 receives the AND signal 2a
-1, it activates the instruction fetch mechanism of the instruction control unit 11, and operates to open the fetch request path (address bus in FIG. 1) for instruction prefetching at timing T3, for example. (See "Instruction Prefetch OK" in Figure 2).

After that, the instruction prefetch (in Figure 2,
IFRQ,, ) is performed, but the storage control unit (SCU) 2 requests the instruction processing unit (IPU) 1 to
For example, at timing T5, by sending out a signal 2a-2 activated by a move-in start signal, which is a data transfer start signal from the main memory, as a signal indicating that the request operand can be transferred. The prefetch operation of the above instruction is interrupted, the operation returns to the inhibited instruction processing, and operand fetch requests (OPRQ) (B), (C), ... are sent to the above fetch request path. It becomes like this.

As described above, in the present invention, in a memory access method in which both an instruction fetch request (IFRQ) and an operand fetch request (OPRQ) are performed using the same path, the instruction processing unit (IPU) 1 (OPRQ) is sent to the above-mentioned shared fetch request path, and focusing on the fact that when BS missing is detected, instruction execution in the instruction processing unit (IPU) is suppressed, the above-mentioned fetch request path is The feature is that it is opened and allows prefetching of commands.

〔Effect of the invention〕

As described above in detail, the instruction prefetch method of the present invention is effective when an instruction processing unit (IPU) issues a fetch request to a storage control unit (SCU) having a buffer storage device (BS). In a storage access method that uses the same path for both an operand fetch request (IFRQ) and an operand fetch request (OPRQ), an operand is sent from the instruction processing unit (IPU) to an operand that does not exist in the buffer storage device (BS). When a fetch request (OPRQ) is made, an interlock is applied to the instruction processing unit (IPU), and while operation in the instruction processing unit (IPU) is suppressed, the fetch path is opened. Since it enables instruction fetching during interlock, the instruction buffer in the instruction execution section of the instruction processing unit (IPU) is reduced.
It has the effect of reducing the frequency of empty spaces.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the instruction prefetch operation when the present invention is implemented, and FIG. 3 is a diagram showing the prefetch state of the instruction buffer. Figure 4 is a diagram explaining the storage access method in a conventional pipeline control computer system, Figure 5 is a time chart showing the operation of the conventional storage access method, and Figure 6 is a diagram explaining the conventional storage access method. FIG. 2 is a diagram illustrating problems with the technology. In the drawing, 1 is an instruction processing unit (IPU);
1 is an instruction control unit, 12 is an instruction execution unit, 2 is a storage control unit (SCU), 21 is a buffer storage unit (BS),
22 is a control unit, 2a is an instruction prefetch control signal during interlock, T0, T1, ... are timings, (A), (B), (C), ... are operand fetch requests, ,,,... are The command fetch request is shown respectively.

Claims (1)

[Claims] 1. A storage control unit (SCU) 2 has a buffer storage device (BS) 21, and an instruction fetch request (IFRQ) from an instruction processing unit (IPU) 1 to the storage control unit (SCU) 2 is provided. , and an operand fetch request (OPRQ) using the same route, and transmits the request contents to the buffer storage device (BS) 2.
When an operand fetch request (OPRQ) is received from instruction processing unit (IPU) 1 for an operand that does not exist in storage control unit (SCU)
2 interlocks an instruction processing unit (IPU) 1 and inhibits the operation of the instruction processing unit (IPU) 1. During the interlock, the operand is transferred from the main storage to the buffer storage. (BS) Instructs to open the fetch request path if the operand fetch request is being accepted until it is transferred to 21 and the cause of the interlock is buffering due to the operand fetch request. An open instruction means 2a-1 is provided for sending out an open instruction signal, and the instruction control unit 11 in the instruction processing unit (IPU) 1 is controlled by the release instruction signal to perform an instruction fetch even during the interlock. An instruction prefetch method characterized by: