JPS56153420A - Information processor - Google Patents

Information processor

Info

Publication number
JPS56153420A
JPS56153420A JP5632480A JP5632480A JPS56153420A JP S56153420 A JPS56153420 A JP S56153420A JP 5632480 A JP5632480 A JP 5632480A JP 5632480 A JP5632480 A JP 5632480A JP S56153420 A JPS56153420 A JP S56153420A
Authority
JP
Japan
Prior art keywords
register
cpu
devices
interruption
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5632480A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5632480A priority Critical patent/JPS56153420A/en
Publication of JPS56153420A publication Critical patent/JPS56153420A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To transfer data only to the I/O control device that is an object by providing a register for holding the numbers of the I/O control devices to a device connecting I/O devices of the same kind to a CPU or the like by way of corresponding I/O control units. CONSTITUTION:I/O devices are connected to a CPU or IOP by way of corresponding I/O control devices A3, B4, and a single I/O processing program is stored in a memory. At the time when the CPU or IOP performs data transfer, a start program is read out and the number of the device 3 or 4 which is the receiver of the transfer is set in a register R1 then an FF1 is set at 0, thereby inhibiting interruption. The device to be transferred with data is controlled by the combination of the register R1, inverter G9, gates G1-G8. For example, the I/O device corresponding to the unit A3 is started and the FF1 is set at 1. Next, the interruption processing program is read out, and after the register R1, FF1 are set, interruption takes place.
JP5632480A 1980-04-30 1980-04-30 Information processor Pending JPS56153420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5632480A JPS56153420A (en) 1980-04-30 1980-04-30 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5632480A JPS56153420A (en) 1980-04-30 1980-04-30 Information processor

Publications (1)

Publication Number Publication Date
JPS56153420A true JPS56153420A (en) 1981-11-27

Family

ID=13023989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5632480A Pending JPS56153420A (en) 1980-04-30 1980-04-30 Information processor

Country Status (1)

Country Link
JP (1) JPS56153420A (en)

Similar Documents

Publication Publication Date Title
JPS5326539A (en) Data exchenge system
JPS5338373A (en) Ic for watch
JPS56153420A (en) Information processor
JPS56153421A (en) Information processor
JPS5424553A (en) Control system for data transfer
JPS5587220A (en) Interface controller
JPS57101925A (en) Data processing system having asynchronous interface
JPS55125598A (en) Restoration system of memory content
JPS56168256A (en) Data processor
JPS5750378A (en) Control system of data processor
JPS6429946A (en) Data processor
JPS57203162A (en) One-chip microcomputer
JPS576967A (en) Data transfer system
JPS56114026A (en) Data processor
JPS54146542A (en) Priority deciding device
ES8103407A1 (en) Data processing system
JPS5714958A (en) Data processor
JPS6476343A (en) Cache memory control system
JPS5350628A (en) Information processing system
JPS54133851A (en) Data transfer controller
JPS5256830A (en) Dma system of microcomputer
JPS55108068A (en) Memory control system
JPS648470A (en) Input/output controller
JPS54154235A (en) Data process system containing peripheral unit adaptor
JPS5447538A (en) Channel device