JPS56153421A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS56153421A JPS56153421A JP5632580A JP5632580A JPS56153421A JP S56153421 A JPS56153421 A JP S56153421A JP 5632580 A JP5632580 A JP 5632580A JP 5632580 A JP5632580 A JP 5632580A JP S56153421 A JPS56153421 A JP S56153421A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- register
- cpu
- control devices
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To transfer data only to the device that is an object by providing a register with degrees of priority holding the numbers of I/O control devices to a unit connecting I/O devices of the same kind to a CPU or the like by way of corresponding I/O control devices. CONSTITUTION:I/O devices are connected to a CPU or IOP by way of corresponding I/O control devices A3, B4, and a single I/O processing program is stored in a memory. At the time when the CPU or IOP performs data transfer, a start program is read out and the number of the device 3 or 4 which is the receiver of the transfer is set in a register R1; also, an FF1 is set at 0, thereby inhibiting interruption. For example, the I/O device corresponding to the device A3 is started, and the FF1 is set at 1. Next, the interruption processing program is read out, and after the register R1 and the FF1 are set, interruption takes place. When at this time, the units A3, B4 generate interruption simultaneously, the device A3 is given preference.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5632580A JPS56153421A (en) | 1980-04-30 | 1980-04-30 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5632580A JPS56153421A (en) | 1980-04-30 | 1980-04-30 | Information processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56153421A true JPS56153421A (en) | 1981-11-27 |
Family
ID=13024021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5632580A Pending JPS56153421A (en) | 1980-04-30 | 1980-04-30 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56153421A (en) |
-
1980
- 1980-04-30 JP JP5632580A patent/JPS56153421A/en active Pending
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