JPS6491264A - Data transfer controller - Google Patents

Data transfer controller

Info

Publication number
JPS6491264A
JPS6491264A JP24834087A JP24834087A JPS6491264A JP S6491264 A JPS6491264 A JP S6491264A JP 24834087 A JP24834087 A JP 24834087A JP 24834087 A JP24834087 A JP 24834087A JP S6491264 A JPS6491264 A JP S6491264A
Authority
JP
Japan
Prior art keywords
data
data transfer
controller
transfer controller
storage places
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24834087A
Other languages
Japanese (ja)
Inventor
Yukio Uchiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24834087A priority Critical patent/JPS6491264A/en
Publication of JPS6491264A publication Critical patent/JPS6491264A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To reduce the quantity of hardware and to simplify control by providing a storage means having N-number of storages which respectively have plural storage places. CONSTITUTION:A system memory 1 having plural storage places in which data one word can respectively be stored, a data transfer controller 3, a system bus consisting of plural signal lines connecting the system memory 1 and the data transfer controller 3, and a peripheral device connected with the controller 3 are given. The controller 3 consists of a data handling circuit 4 connected with the system bus 2, a local memory part 5 having plural storage places which can respectively store data of one byte and a second local memory part 6 having plural storage places which can respectively store data of one byte, an address arithmetic circuit 8, an address circuit 7 and a DMA control circuit.
JP24834087A 1987-09-30 1987-09-30 Data transfer controller Pending JPS6491264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24834087A JPS6491264A (en) 1987-09-30 1987-09-30 Data transfer controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24834087A JPS6491264A (en) 1987-09-30 1987-09-30 Data transfer controller

Publications (1)

Publication Number Publication Date
JPS6491264A true JPS6491264A (en) 1989-04-10

Family

ID=17176629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24834087A Pending JPS6491264A (en) 1987-09-30 1987-09-30 Data transfer controller

Country Status (1)

Country Link
JP (1) JPS6491264A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6288031A (en) * 1985-10-14 1987-04-22 Nec Corp Register filing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6288031A (en) * 1985-10-14 1987-04-22 Nec Corp Register filing system

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