JPS5667430A - Dma control device - Google Patents
Dma control deviceInfo
- Publication number
- JPS5667430A JPS5667430A JP14400379A JP14400379A JPS5667430A JP S5667430 A JPS5667430 A JP S5667430A JP 14400379 A JP14400379 A JP 14400379A JP 14400379 A JP14400379 A JP 14400379A JP S5667430 A JPS5667430 A JP S5667430A
- Authority
- JP
- Japan
- Prior art keywords
- input
- data
- controller
- output device
- dma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To increase the high speed and extensive nature, by giving the processing functions such as the retrieval and pickup of data in an input and output device to a direct access control device DMA, in addition to the data transfer between input and output devices and main memory devices.
CONSTITUTION: A main memory device 3 and an input and output device having a DMA controller 2 and a DMA mode selector circuit 1 are connected via a system bus 6, and a buffer 4 to store the transfer data is connected to a controller 2 of the input and output device. The selection circuit 1 is provided with a mode selection register 11, FF12 and gate 13, and a floppy disc controller 7 and a register 8 are connected to the selection circuit 1. Further, the request REQ of the controller 7 is input with the selection circuit 1 to decide whether or not the data transfer is made via the buffer 4, enabling the retrieval and pickup processing of data in addition to the data transfer to increase the high speed and extension performance of the input and output device.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14400379A JPS5667430A (en) | 1979-11-07 | 1979-11-07 | Dma control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14400379A JPS5667430A (en) | 1979-11-07 | 1979-11-07 | Dma control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5667430A true JPS5667430A (en) | 1981-06-06 |
Family
ID=15352046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14400379A Pending JPS5667430A (en) | 1979-11-07 | 1979-11-07 | Dma control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5667430A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4929536A (en) * | 1972-07-14 | 1974-03-16 | ||
JPS5142438A (en) * | 1974-10-09 | 1976-04-10 | Hitachi Ltd | |
JPS5384632A (en) * | 1976-12-30 | 1978-07-26 | Honeywell Inf Systems | Output*input cache system |
-
1979
- 1979-11-07 JP JP14400379A patent/JPS5667430A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4929536A (en) * | 1972-07-14 | 1974-03-16 | ||
JPS5142438A (en) * | 1974-10-09 | 1976-04-10 | Hitachi Ltd | |
JPS5384632A (en) * | 1976-12-30 | 1978-07-26 | Honeywell Inf Systems | Output*input cache system |
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