JPS6422141A - Transmission control system - Google Patents
Transmission control systemInfo
- Publication number
- JPS6422141A JPS6422141A JP17835587A JP17835587A JPS6422141A JP S6422141 A JPS6422141 A JP S6422141A JP 17835587 A JP17835587 A JP 17835587A JP 17835587 A JP17835587 A JP 17835587A JP S6422141 A JPS6422141 A JP S6422141A
- Authority
- JP
- Japan
- Prior art keywords
- address
- reading
- writing
- page
- condition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To prevent the inversion of a writing address and a reading address from being generated by supervising the writing condition and reading condition of a buffer memory and controlling the transfer speed of an input/output in accordance with the accumulating condition of a packet. CONSTITUTION:At a supervising circuit 201, the reading page and address of output interface circuits 1111-111N to read and transfer the packet while it is presently written in a buffer memory 108 are compared with the writing page and address by comparators 203 and 204. When both pages are coincident and the writing address precedes the reading address, the writing is prohibited. Further, the writing page and address of input interface circuits 1101-110N where the data of the packet during the present reading come in are compared with the reading page and address with comparators 213 and 214, and when both pages are coincident and the reading address precedes, the reading is prohibited.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17835587A JPS6422141A (en) | 1987-07-17 | 1987-07-17 | Transmission control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17835587A JPS6422141A (en) | 1987-07-17 | 1987-07-17 | Transmission control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6422141A true JPS6422141A (en) | 1989-01-25 |
Family
ID=16047040
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17835587A Pending JPS6422141A (en) | 1987-07-17 | 1987-07-17 | Transmission control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6422141A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008022399A (en) * | 2006-07-14 | 2008-01-31 | Auto Network Gijutsu Kenkyusho:Kk | Relay connection unit |
JP2008135068A (en) * | 2000-08-29 | 2008-06-12 | Agere Systems Guardian Corp | Shared device and memory using split bus and time slot interface bus arbitration |
JP2012191659A (en) * | 2012-06-06 | 2012-10-04 | Auto Network Gijutsu Kenkyusho:Kk | Relay connection unit |
-
1987
- 1987-07-17 JP JP17835587A patent/JPS6422141A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008135068A (en) * | 2000-08-29 | 2008-06-12 | Agere Systems Guardian Corp | Shared device and memory using split bus and time slot interface bus arbitration |
JP2008022399A (en) * | 2006-07-14 | 2008-01-31 | Auto Network Gijutsu Kenkyusho:Kk | Relay connection unit |
JP2012191659A (en) * | 2012-06-06 | 2012-10-04 | Auto Network Gijutsu Kenkyusho:Kk | Relay connection unit |
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