JPS6415844A - Memory device - Google Patents

Abstract

PURPOSE:To increase the write processing speed by adding a complement to the end of the data when this data is written to write the complement to a cache memory and adding the data read out of the cache memory to check the propriety. CONSTITUTION:When a writing instruction is given from a host device, a transfer control circuit 1 receives data from the host device and gives an instruction to a memory control circuit 2 to write the data into a cache memory 3. At the same time, the circuit 1 gives an instruction to an adder to adds those received data together. When the transfer of data is through, the circuit 1 receives the complement of the addition result from a complement device 5 for addition of said complement to the end of the data and then writes the value of the complement into the memory 3 via the circuit 2. Then the circuit 1 reads the data including the one added in a write mode. Furthermore the circuit 1 gives an instruction to the adder 4 to add the read data together. Then the circuit 1 checks the result of the adder 4 at the end of the transfer of data and ends normally the transfer of data when the result of the adder 4 is equal to zero.