JPS6488641A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6488641A
JPS6488641A JP62245003A JP24500387A JPS6488641A JP S6488641 A JPS6488641 A JP S6488641A JP 62245003 A JP62245003 A JP 62245003A JP 24500387 A JP24500387 A JP 24500387A JP S6488641 A JPS6488641 A JP S6488641A
Authority
JP
Japan
Prior art keywords
address
bits
correction
data
request signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62245003A
Other languages
Japanese (ja)
Inventor
Masaharu Ejiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62245003A priority Critical patent/JPS6488641A/en
Publication of JPS6488641A publication Critical patent/JPS6488641A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To use an idle time of a main storage device and to execute a partial write with minimum redundancy bits for one word length without impairing the processing performance of the titled processor by holding an address where a write is partially executed, and starting the correction with a correction request signal. CONSTITUTION:When a correction request signal 13 is inputted from a control part 24, a timing control circuit 28 is activated, a 32-bit data is read out from an address in an address holding circuit 25, redundancy data in seven bits for the read data is generated, the thirty-two and the seven bits (data + redundancy bits) are written in a memory chip part 23, and the content of the address holding register 25 which is a partial write register is erased. By the activation of the correction request signal 13, the correction of the redundancy bits of an address partially written in the idle time of the main storage device 2 is possible. As a result, a partial write is enabled with the minimum redundancy bits for one word length.
JP62245003A 1987-09-29 1987-09-29 Information processor Pending JPS6488641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245003A JPS6488641A (en) 1987-09-29 1987-09-29 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245003A JPS6488641A (en) 1987-09-29 1987-09-29 Information processor

Publications (1)

Publication Number Publication Date
JPS6488641A true JPS6488641A (en) 1989-04-03

Family

ID=17127131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245003A Pending JPS6488641A (en) 1987-09-29 1987-09-29 Information processor

Country Status (1)

Country Link
JP (1) JPS6488641A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2640402A1 (en) * 1988-12-08 1990-06-15 Nec Corp Memory control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2640402A1 (en) * 1988-12-08 1990-06-15 Nec Corp Memory control device

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