JPS5750039A - Computer system - Google Patents

Computer system

Info

Publication number
JPS5750039A
JPS5750039A JP12515680A JP12515680A JPS5750039A JP S5750039 A JPS5750039 A JP S5750039A JP 12515680 A JP12515680 A JP 12515680A JP 12515680 A JP12515680 A JP 12515680A JP S5750039 A JPS5750039 A JP S5750039A
Authority
JP
Japan
Prior art keywords
computer
memory
bus
data
dma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12515680A
Other languages
Japanese (ja)
Inventor
Yasutaka Yamane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12515680A priority Critical patent/JPS5750039A/en
Publication of JPS5750039A publication Critical patent/JPS5750039A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To raise the responsiveness and efficiency of a system, by connecting different kinds of computers by a direct memory access system. CONSTITUTION:The titled system is provided with a direct memory access (DMA) bus 1, and a host computer 2 and a slave computer 3, having main memories 2M, 3M, which are both connected to said bus 1. Also, it is provided with a memory control means 4 which is started by one computer and transfers a data stored in the main memory of one computer to the main memory of the other computer through said but 1 by means of DMA. In this way, for instance, a processor part 2P of the host computer 2 sets a data to the transferred, to the memory part 2M, and sends a data transfer request to a processor part 3P of the slave computer 3 through an interruption control device 8. The processor part 3P which has received this request starts the device 4, and the device 4 transfers a data of the memory part 2M to the memory part 3M through the bus 1.
JP12515680A 1980-09-09 1980-09-09 Computer system Pending JPS5750039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12515680A JPS5750039A (en) 1980-09-09 1980-09-09 Computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12515680A JPS5750039A (en) 1980-09-09 1980-09-09 Computer system

Publications (1)

Publication Number Publication Date
JPS5750039A true JPS5750039A (en) 1982-03-24

Family

ID=14903255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12515680A Pending JPS5750039A (en) 1980-09-09 1980-09-09 Computer system

Country Status (1)

Country Link
JP (1) JPS5750039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61128302A (en) * 1984-11-28 1986-06-16 Omron Tateisi Electronics Co Programmable controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61128302A (en) * 1984-11-28 1986-06-16 Omron Tateisi Electronics Co Programmable controller

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