JPS5697121A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS5697121A
JPS5697121A JP17172279A JP17172279A JPS5697121A JP S5697121 A JPS5697121 A JP S5697121A JP 17172279 A JP17172279 A JP 17172279A JP 17172279 A JP17172279 A JP 17172279A JP S5697121 A JPS5697121 A JP S5697121A
Authority
JP
Japan
Prior art keywords
bus
processor
local bus
microprocessors
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17172279A
Other languages
Japanese (ja)
Inventor
Shigeru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17172279A priority Critical patent/JPS5697121A/en
Publication of JPS5697121A publication Critical patent/JPS5697121A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To increase the efficiency of data transfer, by transiting the access request which is made from a plurality of processors at the same time to other local bus on the way of information transfer sequence, in the device in which a plurality of microprocessors are connected to the common bus.
CONSTITUTION: When a plurality of microprocessors 1 and 2 are connected to the common bus C-BUS connected to the main storage unit 3, and each processor 1 is provided with the local bus driver and receiver 1-2 which operates as the data transmission and reception section between the processor 1 and the main memory unit 3. Further, the local bus control section 1-1 is connected to the processor 1, the output ALEO is fed to the common bus control section 4 consisting of the timing generator 4-1 and the control-over judgement circuit 4-2, and this output is connected to C-BUS via the bus driver and receiver 5. With this constitution, the information is transferred to the local bus on the way of transfer, allowing to give margin to C-BUS.
COPYRIGHT: (C)1981,JPO&Japio
JP17172279A 1979-12-29 1979-12-29 Bus control system Pending JPS5697121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17172279A JPS5697121A (en) 1979-12-29 1979-12-29 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17172279A JPS5697121A (en) 1979-12-29 1979-12-29 Bus control system

Publications (1)

Publication Number Publication Date
JPS5697121A true JPS5697121A (en) 1981-08-05

Family

ID=15928448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17172279A Pending JPS5697121A (en) 1979-12-29 1979-12-29 Bus control system

Country Status (1)

Country Link
JP (1) JPS5697121A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60179842A (en) * 1984-02-28 1985-09-13 Fujitsu Ltd Bus system of service processor
JPS61216074A (en) * 1985-02-14 1986-09-25 Fujitsu Ltd Direct memory access system
JPS6341973A (en) * 1986-08-07 1988-02-23 Nec Corp Multi-processor system
JPH05242015A (en) * 1992-01-02 1993-09-21 Internatl Business Mach Corp <Ibm> Computer system and method for storing transfer data between its system memory and input/output device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60179842A (en) * 1984-02-28 1985-09-13 Fujitsu Ltd Bus system of service processor
JPH0345410B2 (en) * 1984-02-28 1991-07-11 Fujitsu Ltd
JPS61216074A (en) * 1985-02-14 1986-09-25 Fujitsu Ltd Direct memory access system
JPS6341973A (en) * 1986-08-07 1988-02-23 Nec Corp Multi-processor system
JPH0575140B2 (en) * 1986-08-07 1993-10-19 Nippon Electric Co
JPH05242015A (en) * 1992-01-02 1993-09-21 Internatl Business Mach Corp <Ibm> Computer system and method for storing transfer data between its system memory and input/output device

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