JPS5667429A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS5667429A
JPS5667429A JP14400079A JP14400079A JPS5667429A JP S5667429 A JPS5667429 A JP S5667429A JP 14400079 A JP14400079 A JP 14400079A JP 14400079 A JP14400079 A JP 14400079A JP S5667429 A JPS5667429 A JP S5667429A
Authority
JP
Japan
Prior art keywords
circuit
parity
data
constitution
information processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14400079A
Other languages
Japanese (ja)
Inventor
Kazutomi Tamai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14400079A priority Critical patent/JPS5667429A/en
Publication of JPS5667429A publication Critical patent/JPS5667429A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To reduce the number of parity circuits and to simplify the system constitution, by providing a parity circuit with the CPU of system performing the transmission and reception of direct data between the memory device and the direct memory access device.
CONSTITUTION: The transmission and reception of data is directly made between the memory units 2, 3 and direct memory access devices 4, 5 via a bidirectional data bus 6 under the control of a CPU1. A parity check circuit PC11 and 1 or a parity bit generating circuit 12 are provided in CPU1 of this information processing system. The parity check of transfer data transferred on the bus 6 is made at the circuit PC11, the circuit PC12 produces the parity bit to the transferred data, simplifying the system constitution through the reduction of the parity circuit of system.
COPYRIGHT: (C)1981,JPO&Japio
JP14400079A 1979-11-07 1979-11-07 Information processing system Pending JPS5667429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14400079A JPS5667429A (en) 1979-11-07 1979-11-07 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14400079A JPS5667429A (en) 1979-11-07 1979-11-07 Information processing system

Publications (1)

Publication Number Publication Date
JPS5667429A true JPS5667429A (en) 1981-06-06

Family

ID=15351976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14400079A Pending JPS5667429A (en) 1979-11-07 1979-11-07 Information processing system

Country Status (1)

Country Link
JP (1) JPS5667429A (en)

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