JPS57143629A - Input and output control system - Google Patents

Input and output control system

Info

Publication number
JPS57143629A
JPS57143629A JP2880881A JP2880881A JPS57143629A JP S57143629 A JPS57143629 A JP S57143629A JP 2880881 A JP2880881 A JP 2880881A JP 2880881 A JP2880881 A JP 2880881A JP S57143629 A JPS57143629 A JP S57143629A
Authority
JP
Japan
Prior art keywords
input
mupc8
contents
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2880881A
Other languages
Japanese (ja)
Inventor
Seitaro Miyajima
Toshiharu Ogasawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2880881A priority Critical patent/JPS57143629A/en
Publication of JPS57143629A publication Critical patent/JPS57143629A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

PURPOSE:To improve processing performance and to reduce cost by transferring the contents of registers stored with instructions and data to a memory under DMA control, and permitting a microprocessor to retrieve the contents of the memory at a higher speed than that of input and output operation. CONSTITUTION:With regard to input and output instructions and data from a processor 1, a decoding circuit 14 confirms that they are for an input and output control mechanism 6, and an instruction transfer discriminating circuit 15 judges that the input and output instructions are to be transferred, so that they are stored in an instruction register 9 and a data register 10 respectively. Once signals from the circuits 14 and 15 are received by a DMA control circuit 16, a DMA request is sent to a microprocessor muPC8. The muPC8 informs the circuit 16 of DMA acceptance during the idle state of a microprogram being executed. The circuit 16 writes the contents of the registers 9 and 10 in a prescribed area of the memory 11. A timer 19 interrupts the muPC8 at constant intervals of time faster than the operation of an input and output equipment 12, and the muPC8 retrieves the contents of the storage area of the memory 11 to detect the instructions and data, thereby controlling the equipment 12.
JP2880881A 1981-02-28 1981-02-28 Input and output control system Pending JPS57143629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2880881A JPS57143629A (en) 1981-02-28 1981-02-28 Input and output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2880881A JPS57143629A (en) 1981-02-28 1981-02-28 Input and output control system

Publications (1)

Publication Number Publication Date
JPS57143629A true JPS57143629A (en) 1982-09-04

Family

ID=12258712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2880881A Pending JPS57143629A (en) 1981-02-28 1981-02-28 Input and output control system

Country Status (1)

Country Link
JP (1) JPS57143629A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538224A (en) * 1982-09-30 1985-08-27 At&T Bell Laboratories Direct memory access peripheral unit controller
FR2574960A1 (en) * 1984-12-19 1986-06-20 Gradient Module for data exchange between processors linked to this module by a global bus and a peripheral unit linked to this module
JPS62216061A (en) * 1985-11-15 1987-09-22 デ−タ−・ゼネラル・コ−ポレ−シヨン Data processing system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538224A (en) * 1982-09-30 1985-08-27 At&T Bell Laboratories Direct memory access peripheral unit controller
FR2574960A1 (en) * 1984-12-19 1986-06-20 Gradient Module for data exchange between processors linked to this module by a global bus and a peripheral unit linked to this module
JPS62216061A (en) * 1985-11-15 1987-09-22 デ−タ−・ゼネラル・コ−ポレ−シヨン Data processing system

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