JPS54128637A - Control system for cash memory - Google Patents

Control system for cash memory

Info

Publication number
JPS54128637A
JPS54128637A JP3609378A JP3609378A JPS54128637A JP S54128637 A JPS54128637 A JP S54128637A JP 3609378 A JP3609378 A JP 3609378A JP 3609378 A JP3609378 A JP 3609378A JP S54128637 A JPS54128637 A JP S54128637A
Authority
JP
Japan
Prior art keywords
memory
cash
unit
counter
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3609378A
Other languages
Japanese (ja)
Inventor
Takashi Rokutanda
Yoshiyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3609378A priority Critical patent/JPS54128637A/en
Publication of JPS54128637A publication Critical patent/JPS54128637A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform good efficient control, by performing the initialization of the main memory and cash memory and the refresh control of the main memory with one circuit, and changing the handling of the cash memory with the nature of the memory access request.
CONSTITUTION: In the data processing unit having the cash memory, the memory control unit 65 performing initialization of the main memory 2 and cash memory and the refresh operation, is provided, and the unit 65 is provided with the binary counter 61 used as the address register and the flag 64 set until the end of initial set, after the power application of the power supply to the data register 63 and the unit 65. Further, when the power supply is applied to the unit 65, the counter 61 is set, count is up at initial set, and when the flag 64 is set, the output of the counter 61 is fed to the cash memory control section 9 and the memory bus control section 62 to perform write-in for the main memory and cash memory. When the flag 64 is reset, the output of the counter 61 is used for refresh of the main memory.
COPYRIGHT: (C)1979,JPO&Japio
JP3609378A 1978-03-30 1978-03-30 Control system for cash memory Pending JPS54128637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3609378A JPS54128637A (en) 1978-03-30 1978-03-30 Control system for cash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3609378A JPS54128637A (en) 1978-03-30 1978-03-30 Control system for cash memory

Publications (1)

Publication Number Publication Date
JPS54128637A true JPS54128637A (en) 1979-10-05

Family

ID=12460129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3609378A Pending JPS54128637A (en) 1978-03-30 1978-03-30 Control system for cash memory

Country Status (1)

Country Link
JP (1) JPS54128637A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5829061A (en) * 1981-08-17 1983-02-21 Fujitsu Ltd Disc cache controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5829061A (en) * 1981-08-17 1983-02-21 Fujitsu Ltd Disc cache controller
JPH0323939B2 (en) * 1981-08-17 1991-04-02 Fujitsu Ltd

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