JPS57103190A - Refreshment controller for random access memory - Google Patents

Refreshment controller for random access memory

Info

Publication number
JPS57103190A
JPS57103190A JP55180075A JP18007580A JPS57103190A JP S57103190 A JPS57103190 A JP S57103190A JP 55180075 A JP55180075 A JP 55180075A JP 18007580 A JP18007580 A JP 18007580A JP S57103190 A JPS57103190 A JP S57103190A
Authority
JP
Japan
Prior art keywords
refreshment
signal
controller
output
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55180075A
Other languages
Japanese (ja)
Inventor
Akira Hitomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55180075A priority Critical patent/JPS57103190A/en
Publication of JPS57103190A publication Critical patent/JPS57103190A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To shorten the overhead time of memory access, by outputting a refreshment signal repeatedly right before the start of the transfer operation of a DMA controller every time a memory-bus use acknowledge signal is outputted from an arithmetic controller. CONSTITUTION:When a DMA controller sends a bus request to an arithmetic controller, a bus-use acknowledge signal BUSACK is supplied to an FF104 to operate an FF105, whose output is supplied to a multiplier 103; and the output of a counter 102 is sent to a DRAM as a refreshment address signal MADR. Then, the output of an FF106 is converted through an AND gate 107 into a refreshment signal RASREF, which is outputted. The input of the multiplier 103 is switched to the side of a multiplier 101, and the inverted output of the FF105 is supplied to an AND gate 108, whose output is inputted to the counter to update a refreshment address, thereby outputting a refreshment signal repeatedly shortly before the start of DMA transfer in response to every signal BUSACK. Consequently, the overhead time of memory access is shortened.
JP55180075A 1980-12-19 1980-12-19 Refreshment controller for random access memory Pending JPS57103190A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55180075A JPS57103190A (en) 1980-12-19 1980-12-19 Refreshment controller for random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55180075A JPS57103190A (en) 1980-12-19 1980-12-19 Refreshment controller for random access memory

Publications (1)

Publication Number Publication Date
JPS57103190A true JPS57103190A (en) 1982-06-26

Family

ID=16077015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55180075A Pending JPS57103190A (en) 1980-12-19 1980-12-19 Refreshment controller for random access memory

Country Status (1)

Country Link
JP (1) JPS57103190A (en)

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