JPS57197645A - Data transfer control device - Google Patents

Data transfer control device

Info

Publication number
JPS57197645A
JPS57197645A JP8194681A JP8194681A JPS57197645A JP S57197645 A JPS57197645 A JP S57197645A JP 8194681 A JP8194681 A JP 8194681A JP 8194681 A JP8194681 A JP 8194681A JP S57197645 A JPS57197645 A JP S57197645A
Authority
JP
Japan
Prior art keywords
data
address
transfer
reference memory
dmca
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8194681A
Other languages
Japanese (ja)
Inventor
Koji Nagafune
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8194681A priority Critical patent/JPS57197645A/en
Publication of JPS57197645A publication Critical patent/JPS57197645A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0215Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE:To eliminate unnecessary data transfer and improve the efficiency of the use of a system by implementing transfer operation only in the case of requesting for data transfer that is different from the previous one referring to the address data stored in reference memory. CONSTITUTION:As to reference memory that stores an address of (a) transfer data, for instance, it inputs an address data to multiplexers 10 and 11 through an address bus 9, and based on a select signal outputted by a dynamic memory access controller DMCA 5, writes data (f) and (g) in the same contents as the address data in reference memory 12 and 13. Then, if there is a request for transfer from a CPU 3, it stores a transfer display data ''1'' in the address assigned by the address data (f) and (g), and outputs update data (h) and (i) which becomes ''1'' only when a request for transfer is made for a different address by the reference memory 12 and 13, and sends them to a selector 14. Then, it outputs the signal selected by the selector 14 to the DMCA 5 as a read signal (j).
JP8194681A 1981-05-29 1981-05-29 Data transfer control device Pending JPS57197645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8194681A JPS57197645A (en) 1981-05-29 1981-05-29 Data transfer control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8194681A JPS57197645A (en) 1981-05-29 1981-05-29 Data transfer control device

Publications (1)

Publication Number Publication Date
JPS57197645A true JPS57197645A (en) 1982-12-03

Family

ID=13760663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8194681A Pending JPS57197645A (en) 1981-05-29 1981-05-29 Data transfer control device

Country Status (1)

Country Link
JP (1) JPS57197645A (en)

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