JPS553084A - Sequence control circuit - Google Patents

Sequence control circuit

Info

Publication number
JPS553084A
JPS553084A JP7618978A JP7618978A JPS553084A JP S553084 A JPS553084 A JP S553084A JP 7618978 A JP7618978 A JP 7618978A JP 7618978 A JP7618978 A JP 7618978A JP S553084 A JPS553084 A JP S553084A
Authority
JP
Japan
Prior art keywords
sequence control
agreement
associative memory
control circuit
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7618978A
Other languages
Japanese (ja)
Inventor
Masaharu Hirayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7618978A priority Critical patent/JPS553084A/en
Publication of JPS553084A publication Critical patent/JPS553084A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a sequence control circuit which possesses the function with which various branching systems can be realized easily and can give the dynamic alteration to both the branching system and the branching address by adding the associative memory device and the associative memory rewriting device to the sequence control circuit.
CONSTITUTION: At input decision memory part 61, the state information of arithmetic unit 4 is supplied from state information decision line 63, and the contents of sequence control field 32 of microorder register 3 is supplied from sequence control decision line 64. And the agreement or disagreement between each information and the information memorized in part 61 is delivered to agreement signal line 65. The microprogram to be put into control memory address register 2 is memorized in agreement output memory part 62. And when line 56 shows the result of agreement, the address of that microprogram is read out. Part 61 and 62 form associative memory device 6, and the proper contents is written into device 6 via associative memory rewriting circuit 7.
COPYRIGHT: (C)1980,JPO&Japio
JP7618978A 1978-06-22 1978-06-22 Sequence control circuit Pending JPS553084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7618978A JPS553084A (en) 1978-06-22 1978-06-22 Sequence control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7618978A JPS553084A (en) 1978-06-22 1978-06-22 Sequence control circuit

Publications (1)

Publication Number Publication Date
JPS553084A true JPS553084A (en) 1980-01-10

Family

ID=13598171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7618978A Pending JPS553084A (en) 1978-06-22 1978-06-22 Sequence control circuit

Country Status (1)

Country Link
JP (1) JPS553084A (en)

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