JPS5569828A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5569828A
JPS5569828A JP14195178A JP14195178A JPS5569828A JP S5569828 A JPS5569828 A JP S5569828A JP 14195178 A JP14195178 A JP 14195178A JP 14195178 A JP14195178 A JP 14195178A JP S5569828 A JPS5569828 A JP S5569828A
Authority
JP
Japan
Prior art keywords
circuit
access
request
same time
access request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14195178A
Other languages
Japanese (ja)
Inventor
Koji Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14195178A priority Critical patent/JPS5569828A/en
Publication of JPS5569828A publication Critical patent/JPS5569828A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to a user to select an access request on preference basis by signifying one of several priority circuits in accordance with contents of rewritable registers.
CONSTITUTION: Priority circuits 7 and 8 are constituted according to algorithm with priority given to access request sources 1 and 2 respectively. Now, when logic "0" is written in section 13-1 of mode register 13, AND circuit 11 is OFF and AND circuit 10 is ON through NOT circuit 9. Therefore, if access requests are sent from access request sources 1W3 at the same time, a signal from request source 1 is outputted by way of circuit 7, AND circuit 10, and OR circuit 12. Writing logic "1" in section 13-1, however, outputs a signal from request source 2 via circuit 8 when access requests are made by request sources 1W3 at the same time in this state.
COPYRIGHT: (C)1980,JPO&Japio
JP14195178A 1978-11-17 1978-11-17 Data processor Pending JPS5569828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14195178A JPS5569828A (en) 1978-11-17 1978-11-17 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14195178A JPS5569828A (en) 1978-11-17 1978-11-17 Data processor

Publications (1)

Publication Number Publication Date
JPS5569828A true JPS5569828A (en) 1980-05-26

Family

ID=15303915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14195178A Pending JPS5569828A (en) 1978-11-17 1978-11-17 Data processor

Country Status (1)

Country Link
JP (1) JPS5569828A (en)

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