JPS5569828A - Data processor - Google Patents
Data processorInfo
- Publication number
- JPS5569828A JPS5569828A JP14195178A JP14195178A JPS5569828A JP S5569828 A JPS5569828 A JP S5569828A JP 14195178 A JP14195178 A JP 14195178A JP 14195178 A JP14195178 A JP 14195178A JP S5569828 A JPS5569828 A JP S5569828A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- access
- request
- same time
- access request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To enable to a user to select an access request on preference basis by signifying one of several priority circuits in accordance with contents of rewritable registers.
CONSTITUTION: Priority circuits 7 and 8 are constituted according to algorithm with priority given to access request sources 1 and 2 respectively. Now, when logic "0" is written in section 13-1 of mode register 13, AND circuit 11 is OFF and AND circuit 10 is ON through NOT circuit 9. Therefore, if access requests are sent from access request sources 1W3 at the same time, a signal from request source 1 is outputted by way of circuit 7, AND circuit 10, and OR circuit 12. Writing logic "1" in section 13-1, however, outputs a signal from request source 2 via circuit 8 when access requests are made by request sources 1W3 at the same time in this state.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14195178A JPS5569828A (en) | 1978-11-17 | 1978-11-17 | Data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14195178A JPS5569828A (en) | 1978-11-17 | 1978-11-17 | Data processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5569828A true JPS5569828A (en) | 1980-05-26 |
Family
ID=15303915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14195178A Pending JPS5569828A (en) | 1978-11-17 | 1978-11-17 | Data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5569828A (en) |
-
1978
- 1978-11-17 JP JP14195178A patent/JPS5569828A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES361451A1 (en) | Microprogrammed data processing system utilizing improved storage addressing means | |
JPS5569828A (en) | Data processor | |
JPS5451735A (en) | Computer | |
JPS5617449A (en) | Transit address confirmation system | |
JPS5326632A (en) | Common memory control unit | |
JPS5562582A (en) | Data processing system | |
JPS5510614A (en) | Controller | |
SU955062A1 (en) | Device for forming command address | |
JPS57203279A (en) | Information processing device | |
JPS5785162A (en) | Picture memory access control system | |
JPS553084A (en) | Sequence control circuit | |
JPS5577072A (en) | Buffer memory control system | |
JPS5478635A (en) | Data transfer control circuit | |
JPS56129947A (en) | Microprogram controller | |
JPS57204975A (en) | Automatic selecting system for word display for reference | |
JPS5576422A (en) | Terminal unit | |
JPS5783864A (en) | Multiprocessor system | |
JPS54157444A (en) | Memory control system | |
JPS62172457A (en) | Bus connecting device | |
JPS5491031A (en) | Timing controller | |
JPS57197645A (en) | Data transfer control device | |
JPS56166538A (en) | Data transfer control device | |
KR910012928A (en) | Computer memory expansion system | |
JPS55134460A (en) | Address conversion unit | |
JPS5697146A (en) | Instruction fetch control system |