JPS63208965A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve the executing efficiency of a program incorporated into a CPU by stopping the operation of the CPU only when an external access action is carried out by the CPU in a hold accepting state. CONSTITUTION:When a hold request signal HOLD is set at '1', a hold control circuit 2 outputs a hold accepting state signal HLDMD to an access control circuit 12 in the CPU 1 and a hold signal HLD to an external bus interface 3 respectively. When the interface 3 receives the signal HLD, the external bus signal connected to a peripheral chip is set at a high impedance. While the contents of a built-in program memory 11 are continuously executed by the CPU 1 even though the signal HLDM is outputted. However, the operation of the CPU 1 is stopped by the circuit 12 in case external memory access is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention comprises a built-in program memory that stores a program, a CPU that executes calculations according to instructions of the program stored in the built-in program memory, and an external An external bus interface having an external bus signal for accessing a memory, a hold signal, and a signal that receives the hold signal and sets the hold state signal indicating a hold acceptance state and the external bus signal to a high impedance state.

A microcomputer (hereinafter referred to as a microcomputer) is equipped with a hold control circuit that generates a hold control circuit.

(Prior art) In an application system of microcontrollers that share an address bus, data bus, and memory, a CPU that manages the control right of the shared bus issues a bus use request to the CPU, and if granted, a peripheral LSI that uses the bus 0 peripheral LSI where exists
To access memory from the shared bus, the CPU's address bus, data bus, read signals, and write signals (hereinafter referred to as "external bus signals") must be set to high impedance. A hold function is used to disconnect and make it accessible to the peripheral LSI side. Here, a system using a CPU and a DMAC (Direct Memory Access Controller) will be considered as an example of a bus and memory sharing system. FIG. 6 is a block diagram of a DMA system that shares an address bus, data bus, and memory, and FIG. 7 is a timing chart thereof. CPU 60
1 can access the memory 603 by performing external access. On the other hand, when the peripheral bag @604 needs to access the memory 603, the DMAC 602
DMA against! When the DMAC 602 receives the DMA request signal DRQ 8, it issues a hold request signal HOLD to the CPU ao+.
When the CPU 601 receives the hold request signal H00, it sets the external bus signal to high impedance so that the CPU 601 cannot access the memory 603. After that, the CPU 601 sends a hold request signal H
The hold reception notifying that OLD has been accepted sends a signal HLDA to the DMAC 602, and the DMAC 602
When the hold reception is received, the peripheral device 60 receives the signal HLDAM.
DM informing that DMA was accepted for 4
The A reception outputs a signal to the DAC.

DMAC:602 using the hold function as above
uses a shared bus to access memory 6 without going through CPU 601.
Data can be transferred with 03. As a conventional technology, the hold function control circuit (u
PD7809 User's Manual (IEM-8400)
Chapter 11.2).

A conventional hold function control circuit in a CPU will be described below. FIG. 8 is a block diagram of a conventional microcomputer with a hold control function. The CPU executes calculations according to the contents of the built-in program memory 11. Other C
PU is an access control circuit that performs memory access control +
Equipped with 2A. When an external access signal is output from the access control circuit +2A, the external bus interface 3 outputs the contents of the CPU internal address bus/data bus 4 via the address bus/data bus 4 and uses the read signal surface or write signal WR. Access the external peripheral bag Mli. When the hold request signal HOLD becomes 1'', the hold control circuit 2A sends a status signal HLDMO to the CPU to notify that a hold request has occurred, and generates a hold signal (hold signal) ILO to the external bus interface 3 (hereinafter referred to as hold control). The state in which the circuit 2A generates the hold request signal HLDMO to the CPU + and the hold signal HLD to the external bus interface 3 is referred to as the "hold acceptance state". When the CPU receives the hold acceptance state signal HLDMD, it accepts the hold of the CPU1. is fixed at the state T MLO indicating the state, and stops the operation of the CPU and immediately stops the execution of all programs.Furthermore, when the external bus interface 3 receives the hold signal 0, it outputs the external bus signals connected to the peripheral chips. When the hold reception state is set, the hold control circuit 2A sets the hold reception signal HLDA to 1 to indicate that it has received the hold request signal HOLD.
Make it ″′.

Figure 9 shows the hold request signal HOLD during program execution.
2 is a timing chart when the hold request signal HOLD changes from "0" to "1" and when the hold request signal HOLD changes from "1" to "0". Now, the machine cycle is T1. T2.
Assume that the state consists of states T3, and T3 is the final state. When the hold request signal HOLD becomes "1", the external bus signal is made high impedance at the final clock of state 3 and transferred to state THLO. At the same time, hold reception sets the signal HLD^ to "1", state T, 4. . Then, the hold request signal HOSH0 is always checked and when the hold request signal HOLD is detected as "0", the hold acceptance signal is set to "0" at the second clock of the next state, and the external bus signal is changed at the final clock. Release the high impedance state and proceed to the next machine cycle.

(Problem to be Solved by the Invention) In the conventional microcontroller equipped with the hold function described above, when the hold request signal HOLD is received, the CPU is immediately stopped and the hold reception becomes the state. External access to the CPU is prohibited in order to use the shared bus and memory, but this also interrupts the execution of internal programs.
In single-chip microcontrollers with built-in program memory, the built-in program can be executed even if the shared bus cannot be used due to the hold reception state.However, in conventional control circuits, the CPU operation is stopped, so the execution of the built-in program is efficient. The disadvantage is that the value decreases.

[Means for solving problems]

The microcomputer of the present invention has an access control circuit that stops the operation of the CPU only when an external access operation by the CPU is detected during the hold acceptance state.

[For production]

When a hold signal is received, the external bus signal becomes high impedance, but instead of stopping CPU execution, it does not stop CPU operation until the CPU executes an external access operation, improving the execution efficiency of internal programs. .

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is an overall block diagram of an embodiment of a microcomputer according to the present invention. This embodiment differs from the conventional example shown in FIG. 8 in that the operation of the access control circuit 12 and the hold control circuit from the access control circuit 12 The hold reception to 2 is where the state prohibition signal 01SHLD is added. The hold reception state prohibition signal 0ISHLD is a signal that prevents the hold control circuit 2 from outputting the hold reception state signal HLDMO. Since the other functions are the same, the explanation will be omitted.

Fig. 2 is a detailed diagram of the access control circuit 12, Fig. 3 is a detailed diagram of the hold control circuit 2, Fig. 4 is a detailed diagram of the external bus interface 3, and Fig. 5 is the circuit operation of Figs. 2 and 3. FIG. φ] and φ2 are two-phase system clocks.

The access control circuit 12 includes AND gates 101 . +02
゜+04j09.110,113 and inverter 103
．． 108, or gates 105, 112, and latch 10
6,107. It is composed of IN. The hold control circuit 2 includes latches 301 to 305, 312, 313, and RS
Flip flop 304, 306 and AND gate 3
07.309.311, NOR gate 308.310, and other gate circuits. The external bus interface 3 includes an inverter 401, AND gates 402 and 403, and three-state buffers 404 to 4.
It consists of 08.

First, regarding the access control circuit 12 and the hold control circuit 2 when the hold request signal HOLD is generated during execution of a program stored in the built-in program memory 11, the detailed diagram of the access control circuit 12 in FIG. 2 and the detailed diagram of the access control circuit 12 in FIG. This will be described using a detailed diagram of the hold control circuit 2 and a timing chart in FIG.

Now, in cycle M2, when the system clock φ1 is "1", the hold request signal)10LD;/)("O"
Suppose that the value changes from 1 to 1. Then, the d output of the latch 301 becomes "1" at the next system clock Φ2 (cycle M2), the Q output of the latch 301 is latched by the latch 302 at the next system clock Φ1 (cycle M3), and the next system clock - It is latched by the latch 303 at νriφ2 (cycle M3). Since the hold request signal H0 is "1" for two clocks, both the d output of the latch 301 and the d output of the latch 303 become "1", the output of the AND gate 307 becomes "1", and the next system clock φ1 (Cycle M4) RS flip-flop 304
is set. If, on the other hand, the hold request signal HOLO
If is "0" for two clocks, both the Q output of latch 301 and the Q output of latch 303 are "0", the output of NOR gate 308 is "1", and the next system clock φ1
Then, the RS flip-flop 304 is reset. Currently, the hold request signal HOLD is “1” for 2 clocks and RS
Consider a case where flip-flop 304 is set and an external access instruction is not being executed. Since the external access request signal SLEXM is “0”, the AND gate ++
The output DISHLD of 0 becomes “0” and the NOR gate 31
The output of 0 becomes "1". Then, in the next system clock 2 (cycle M4), the Q output of the latch 312 becomes “1”.
, at the next system clock φ1 (cycle M5), the C output of the latch 313, that is, the hold acceptance is the state signal HL.
OMO becomes "1". Roughly speaking, the C output of the latch 305 becomes “0” at the next system clock φ2 (cycle M5).
As a result, the hold signal HLD becomes "0".

At the next system clock φ1, the hold reception signal HLDA, which is the output of the latch 306, becomes "1". When the hold signal (hold signal) ILD becomes "0", the output of the inverter 401 becomes "1", and the data in timing and data in If the timing is “1”, AND gate 402.4
Since the output of 03 becomes "1", the data bus connected to tristate buffers 404 and 405 becomes high impedance. In this way, the built-in program memory 1
When the program stored in 1 is executed, the hold reception status is immediately changed to the hold reception status as soon as the hold request signal HOLD is generated. In addition, for hold reception, the status signal HLDMO is "
Even if the external access request signal SLEXM is “0”
”, the output of the AND gate 109 is “0” and the C output of the latch 111 is also “0”. Therefore, the CPU
The two-phase operating clock CK1. 2 to C is or gate 11
2. System clock φ1 via AND gate 113
．． ．． It is output in phase with t+2. Therefore, even if the hold reception is in the state, the CPU continues to operate.

Next, we will discuss the case where an external memory access occurs during the hold reception state. Generally, external memory access requires three cycles or more due to the standards for external memory access signals and the standards for closing when accessing the memory.

Assuming that an external access instruction is output from the program memory 11 at the timing of system clock φ1 of cycle M6, the CPU outputs the system clock small 1 (cycle M
6), outputs an external access request signal SLEXM. When the external access request signal SLEXM becomes "1", the hold reception is performed because the status signal HLDMO is "1" and the output of the inverter 10 is "1", so the output of the AND gate 109 becomes "1", and the system clock Φ1 of cycle M6 The C output of the second circuit 111 is 1''.

Therefore, the output of the OR gate 112 is 1", the output of the AND gate 113 is O", and the C
The PU clock CKI is 1", and the clock C is 0". As described above, while the C output of the latch 111 is "1", the CPU clock C is fixed at 1 +" and C is fixed at 0", so the CPU 1 stops operating. Since the hold reception is in this state, the external access request signal S
Even if LEXM tfi is "1", the external access signal is not output and the hold reception status continues. Therefore, during the cycle in which the system clock φ1 of cycle M6 is "1", the hold request signal HOLD changes from "1" to "1". 0”, the next system clock φ2 (cycle M
6), the d output of the latch 301 becomes "0", and the d output of the latch 302 becomes "0" at the next system clock φ1 (cycle M7).
The output becomes "0", and the C output of the latch 303 becomes "0" at the next system clock φ2 (cycle M7), 2
When the inter-clock hold request signal HOLD is 0'', the output of the NOR gate 308 becomes ``1'', and the RS flip-flop 30 is activated at the next system clock φ1 (cycle M8).
4 is reset. The output of Noah gate 310 is “0”
Therefore, the next system clock φ2 (cycle M8
), the C output of the latch 312 becomes 0", and at the next system clock φ1 (cycle M9), the C output of the latch 313, that is, the hold reception status signal HLDMO becomes "0". The 0th order system clock φ2 (cycle M9) The output Q of the latch 305 becomes 1, and the hold signal HLD becomes 1.
'' is output. This releases the high impedance of the external bus signal. Also, when the hold reception status signal HLDMO becomes "0", the 88 flip-flop 306 is reset, so the hold reception is performed by the signal HL.
For the D^ signal, system clock φ1 in cycle M9 is “1”.
”, the hold acceptance state ends as 0 or more, where 2<0 during the system clock.

Next, the operation of the access control circuit 12 during external access will be described. In FIG. 2, for hold reception, when the status signal HLDMO becomes "0", the output of the AND gate 109 becomes "0" and the system clock φ of cycle M9
1, the C output of the latch 111 becomes “0”, and the C output becomes “1”.
become. Also, since the output of the AND gate 101 is "1" and the output of the inverter 10 is "1", the output of the AND gate 102 is also "1", and the output of the OR gate 105 is also "1". While the system clock φ1 is "1", the Q output of the latch 106 is "nl"
, the Q output is "0", therefore, the OR gate 11
The output of 2 is “1”, and the output of AND gate 113 is “0”
So, 1 is for the CPU operating C that runs the old CP.
1", and 2 becomes "0" in C. As described above, latch 10
While the Q output of 6 is “1”, 1 is “I” on the CPU clock C.
”, since 2 is fixed as “0” in C, CPU +
has stopped working. Further, the output DISHLD of the AND gate 110 becomes "1". When the next system clock φ2 is "1" (cycle M9), the output of the latch 107 becomes 1", and the output of the inverter 108 becomes 0". During one cycle of the clock φ2, the ready signal RDY is set to "0" to create the three-state timing necessary for external access. Then, the output of the inverter 103 becomes "1" and the output of the AND gate 104 and the OR gate 105 are set to "1". The output becomes “I”, so 1 in the next system clock (cycle M1
0), the Q output of the latch 106 remains "1" and does not change, so the CPU clock C, LC and 2 are "1", respectively.
2 of the 0-order system clocks fixed at 0 is 1.
When (cycle M10), the ready signal ROY is “1”
Therefore, the output of the AND gate 104 and the output of the OR gate 105 are "0", which is the zero-order system clock φ.
When 1 is "1" (cycle M11), the Q output of the latch 106 is "0".Therefore, in cycle Mfl, 1 in the CPU clock C becomes 1 in the system clock.
The CPU clock C2 operates at the same timing as the system clock φ2. Also, at the timing when 1 in the system clock of cycle Ml+ becomes "1", the AND gate 1
The output of 10 becomes 0''. In this way, external data access is performed.

Next, a case will be described in which there is a conflict between the external access request signal SLEXM and the hold request signal HOLD. When the hold request signal HOLD changes from "0" to "1" during one state of the system clock in cycle M8, the timing T:Rs flip-flop 304 goes through the above-described operation and returns to the timing T:Rs flip-flop 304 in one state of the system clock in cycle MIO. is set. However, the hold reception is a state prohibition signal D.
Since ISHLD is "1", the output of the NOR gate 310 remains "0".
In cycle M11), hold reception is performed by the state prohibition signal DIS.
When the HLD signal becomes "0", the output of the NOR gate 310 becomes "1", and the system clock signal of cycle MI2
For hold reception at link Φ1, status signal HLDMO is “1”
The hold reception is transferred to the state. As described above, in this embodiment, the hold reception state is prohibited from transitioning to the hold reception state by the hold reception state prohibition signal DISHLD until the external data access is completed.

In this embodiment, the operation of external data access and hold reception has been described with respect to the state. It is possible to activate the bus interface and not stop the CPU until external program memory is accessed.

Therefore, in order to prevent the CPU from stopping until the external program memory is accessed, the same control as in the previous embodiment can be performed by using a signal indicating external program memory access instead of the external access request signal SLEXM in FIG.

(Effects of the Invention) As explained above, in the present invention, hold reception is performed only when an external access operation by the CPU occurs during the state.
By stopping the operation of υ′, even if the hold reception state is such that the external bus cannot be used, the internal program will continue to use the CPU until an external access request signal is output from the CPU.
This has the great effect of increasing the execution efficiency of built-in programs without stopping the operation of the PU.

[Brief explanation of the drawing]

1 is a block diagram of one embodiment of the microcomputer of the present invention, FIG. 2 is a detailed diagram of the access control circuit 12, FIG. 3 is a detailed diagram of the hold control circuit 2, and FIG. 4 is a detailed diagram of the external bus interface 3. Figure 5 is an operation timing diagram of the access control circuit 12 and hold control circuit 2, and Figure 6 is a DMA system that shares the bus and memory. 7 is a hold timing diagram, FIG. 8 is a configuration diagram of a conventional example of a microcomputer, and FIG. 9 is a hold control timing diagram of the microcomputer shown in FIG. 1.------cpu, 2.----Hold control circuit, 3..External bus interface, 4..
・Internal address bus/data bus, 11...Program memory, +2--Access control circuit, 106, 107. +11,301,302,303,
305,312.313・・・・・・・・・Latch, 304.306---RS flip flop 0 knob, 1
0t, +02. +04. +09. +10,113.30
7,309.311.402゜403--------AND gate, 105.112---OR gate, 103.40
1-------Inverter, 404.405,406,
4G7, 408 ----- Three-state buffer, to DAC --- Direct memory access reception signal, 0 port 0 --- Direct memory access request signal, HLD − ...Hold signal, HOLO-...Hold request signal, HLDA-...
...Hold reception is a signal, HLDMD--Hold reception is a status signal, DISHLO--Hold reception is a status WBM stop signal, SLEXM--External access request signal, (tll, (t)2-... ...System clock, C1.C'l -----------CPU
'7 C1'7, RDY - Ready signal. Figure 1 Figure 6 ・T・- Route request salt number HOLD A)-Response bus, data bus =======]x--
---
--・Bold HIKI AKA HLDA

Claims (1)

[Claims] A built-in program memory that stores programs, a CPU that executes calculations according to instructions of the programs stored in the built-in program memory, a data bus, an address bus, and read signals for accessing external memory. , an external bus interface having a write signal, a hold request signal, and a hold control circuit that receives the hold request signal and generates a hold state signal indicating a hold acceptance state, a read signal, and a signal that puts the write signal in a high impedance state. A microcomputer comprising: an access control circuit that stops the operation of the CPU only when an external access operation by the CPU is detected during a hold acceptance state.