JPS581256A - Memroy access control system - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a processing system, by reading out of a main storage data from a common bus side in parallel with the readout of data from a cash memory with the processor. CONSTITUTION:A flag f1(READ) is set to a flag 10 with a memroy access request B and a data in a cash memory 2 is read out to the processor 1. When a direct memory access DMA request A(READ) is transmitted from a common bus 7 during the data readout from the memory 2, a reception section 9 receives it to set a flag F1(READ) of a flag 11. The flags 10 and 11 are checked at a discrimination section 12 and while a bit signal H is effective, when the flags F1 and f1 are set, a readout instruction C is transmitted. Thus, the memory control section 4 reads out the data in a memory 5 and transmits it to a bus 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control method for controlling the reading of data in a memory.

A nine-processing system A equipped with an internal storage memory has an internal path and a common (external) path, and D from the common path.
MA1! A method is adopted in which a conflict is determined between a request for memory access and a request for memory access from a processing device, and one of them is given exclusive rights to the internal path.

The conventional method will be explained using figures. Figure 1 is a block diagram explaining the conventional method! D, 1 company processing device, 2#'i cache memory, 3 is internal path, 4 is memory control unit, 5 is memory, 6 is path control unit, 7 is common path% In input/output device, λFiDMA request, B is memory access Ryusu request, d
is data. In FIG. 1, the middle storage memory 2 stores part of the data d in the menu 5.
! 1, the path control unit 6 determines a conflict between the DMA job offer from the common path 7 side and the mesh access request B from the processing device 1, and permits one of them to exclusively use the internal path. In such a processing system, the processing device l
is reading data d from the middle memory 2,
Common path 7 Confucian to DMA l! If a job offer is issued,
If the DMA [request A is READ (output of data from Meminesu 5), the middle Yash memory 2 by processing device IK
In parallel with reading data from the READIII
It is possible to meet the requirements. DMA request is WRITE
In this case, the data in both the cache memory 2 and the memory 5 must be updated, but in the case of REAI, it is only necessary to retrieve the data from the memory 5. If parallel reading is possible in this way, the processing efficiency of the system can be significantly improved.

The present invention focuses on the above points and aims to provide a memory access control method that improves the processing efficiency of a processing system.

For the main line, there is a first control unit that controls a common path connected to input/output devices, a second control unit that controls the main storage device, and a connection between the second control unit and the cache memory. In a data processing system having nine processing devices, while the processing device is extracting data from the cache memory, two requests are made from the common path to the first control unit for a continuous access to data. II.
◎The present invention will be explained below with reference to the drawings. 2.E is an embodiment of the present invention.
This is a professional 11 diagram explaining l, and 9 is a reception part-10,1
1 is a book part, 12 is a discrimination part, C is a read command, H is a hit signal, F, , F, , et al, f.

is 7 lags, and the rest is the same as in FIG. At step 211, 7lags (READ) are set in the shearrag section 10 in response to the memory access request BK from the processing device 1, and the data d in the cache memory 2 is read out to the processing device 1 to be processed. During this continuous output of data from the cache memory 2, a DMA ill request A(R
EAD) is issued, the reception section 9 receives it and
Flag P, (READ) of flag 11 is set. Discrimination unit 12F17') checks the log units 10 and 11, and issues a read command C when the 7 lags F and torato are set while the hit signal H is valid. reads the data in the memory 5 and sends it to the common path 7. On the other hand, the scanning by the processing device 1 and the reading of data/d from the memory 2 continue for the 11th time.

As described above, the present invention enables the main memory data to be read from the common path side in parallel with the scanning by the processing device and the extraction of data from the memory, thereby significantly improving the processing efficiency of the processing system. has advantages.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a conventional system, and FIG. 2 is a block diagram illustrating an embodiment of the present invention. Reference symbols used in the figures are as follows. l is the processing unit, 2 is the cache memory, 3 is the internal path, 4
is a memory control unit, 5 is a memory, 6 is a path control unit, 7 is a common path, 8 is an input/output device, 9 is a reception unit, 10.11 is a flag unit, 12 is a determination unit, A is a DMA request, and B is a Memory access request, C is read command, d is data, E is data bus, F...? , , f, if are flags, and H is a hit signal. No. j[! ] leaf d

Claims (1)

[Claims] a tenth control unit that controls a common bus connected to input/output devices; a second control unit that controls a main storage device;
in a data processing system having a control unit connected to a cache memory, and a processing unit connected to a cache memory, while the processing unit is reading data from the cache memory, 1 transmitting a data read request from the common bus to the first control unit; A memory access control method 0 characterized in that it comprises means for enabling reading of data from the main storage device when a memory access request occurs.