JP3710798B2 - Compound processing unit - Google Patents

Description

  The present invention relates to a composite arithmetic processing device including a plurality of independent arithmetic devices having different (or the same in some cases) characteristics of arithmetic processing, for example, and instructions for the composite arithmetic processing device are derived by a variable program, It is applied to a complex arithmetic processing device to be executed.

The conventional complex arithmetic processing device has a plurality of memories and a plurality of general-purpose registers corresponding to each arithmetic processing device for a plurality of independent arithmetic processing devices, and the first arithmetic processing device to the second arithmetic processing device. When requesting calculation processing for
(1) A method via a shared memory outside a plurality of independent arithmetic processing devices,
(2) The contents of the processing request and the data to be processed are transferred by a method using a data input / output unit such as serial / parallel. In these conventional techniques, the entire processing speed and real-time performance of the arithmetic processing are lost.

Further, when a certain entire process is divided into a plurality of arithmetic processing devices, the superiority or inferiority of the division greatly affects the overall performance. Moreover, the work of dividing the entire process requires very special knowledge and technology.
JP-A-63-3350

In the method of using a plurality of independent arithmetic processing devices in order to improve the arithmetic processing performance in the prior art,
(1) There are a main arithmetic processing device and a sub arithmetic processing device, and the sub arithmetic processing device operates in response to an instruction request from the main arithmetic processing device,
(2) There are two types of methods in which the arithmetic processing is divided into a plurality of blocks, each block is assigned to each arithmetic processing unit, and different processing blocks are executed simultaneously.

  In the case of (1), the time during which the sub processor does not actually operate is long and the efficiency is low (Problem 1).

  In the case of (2), instructions are executed simultaneously and efficiency is high. However, depending on the contents of processing, the division as described above may be extremely difficult, and the divided blocks depend closely on each other. Sometimes it is. When such processing is executed in (2), data transmission / reception occurs frequently between the respective arithmetic processing devices. In such data transmission / reception between the processing units, the higher the frequency and the larger the amount of data, the lower the overall processing speed (Problem 2).

  The interiors of multiple independent arithmetic processing units are designed so that they can be processed individually, and there are unnecessary and redundant parts when viewed in the system of multiple independent arithmetic processing units. However, the cost of the entire system was raised (Problem 3).

  An object of the present invention is to provide a complex arithmetic processing apparatus that solves the above-described problems and can execute arithmetic processing efficiently and inexpensively.

In order to solve the above-described problems, a composite arithmetic processing device of the present invention includes first and second independent arithmetic devices having different characteristics of arithmetic processing, and two ports and the first and second arithmetic devices . A shared memory connected, a shared general-purpose register having two ports connected to the first and second arithmetic units , and the shared memory and shared general-purpose register for accessing the shared memory and the common general-purpose register from the first and second arithmetic units first and second access means, and the interrupt means for generating an interrupt to the second computing device is provided to the first arithmetic unit, the end of the processing by the interrupt provided to the second arithmetic unit Is provided with an arithmetic processing end setting means for informing the first arithmetic device .

When an operation that is more suitable for the processing in the second arithmetic unit occurs in the course of the arithmetic processing, the first arithmetic unit uses the interrupt means to interrupt the second arithmetic unit as a request for the arithmetic processing. The generated data required for the arithmetic processing is stored as an argument in the shared general-purpose register and the shared memory.

The second arithmetic device executes the requested arithmetic processing using an argument, stores the data of the arithmetic result as a return number in the shared general-purpose register and the shared memory, and the arithmetic processing end setting means uses the first arithmetic device. The operation processing end information is set in.

In the above configuration, the shared memory has a rewritable area, and access permission / prohibition information for setting access permission / prohibition information from the first and second arithmetic units for each fixed range of the shared memory and the shared general-purpose register, respectively. Prohibition information setting means may be provided, and access status setting means for transmitting the access status from the first and second arithmetic devices to the second and first arithmetic devices for each fixed range of the shared memory may be provided.

  At this time, the plurality of access means access the shared memory and the shared general-purpose register only for the range where access is permitted while referring to the setting contents of the access permission / prohibition information setting means, and set the access status setting means. The rewritable area of the shared memory is accessed while referring to the contents.

In addition, when the first arithmetic unit requests the second arithmetic unit to calculate, the access status setting means that the setting of the argument is completed when the argument is set in the shared general-purpose register and the shared memory. In addition, the permission / prohibition information of the area holding the argument in the shared general-purpose register and shared memory is reversed by the access permission / prohibition information setting means.

Furthermore, the second arithmetic unit sets, by the access status setting means, that the setting of the return number is completed when the return number is set in the shared general-purpose register and the shared memory when the requested arithmetic processing is completed, The permission / prohibition information of the area holding the return number in the shared general-purpose register and the shared memory is reversed by the access permission / prohibition information setting means.

According to this configuration, when a process suitable for the second arithmetic device occurs in a process block in the first arithmetic device, an operation request is made in the form of an interrupt to another arithmetic device. Other processing can be executed until the calculated operation is completed by the second arithmetic unit. The calculation result of the requested calculation process is held in the shared memory and the shared general-purpose register, and calculation process end information is set. Therefore, when necessary, the first calculation unit checks the calculation process end information and calculates Read the results. Also in the second arithmetic unit, the requested processing is processed within an interrupt, and at the end of the requested arithmetic processing, the arithmetic result and the arithmetic processing end information are set and the processing returns to the main arithmetic processing. At this time, since the requested arithmetic processing is processed in the interrupt, if the processing for saving the shared memory and the general-purpose register used in the main arithmetic unit is incorporated in the initial part of the interrupt arithmetic processing, the main arithmetic processing The requested arithmetic processing can be executed independently without affecting the processing .

According to the complex arithmetic processing device of the present invention, a plurality of independent arithmetic devices that simultaneously process each processing block divided by a plurality of independent arithmetic devices and process a plurality of processing blocks with extremely high dependence transmission and reception between, by using a shared memory and shared general purpose registers, it is possible to perform without performing the transfer of actual data, complicated processing was required multiple computing devices to conventional Necessary arithmetic processing can be realized with an efficient and inexpensive system. In other words, efficient software can be created with efficient hardware.

Further, according to this composite arithmetic processing device, when processing suitable for the second arithmetic device occurs in the process in a certain processing block in the first arithmetic device , the arithmetic operation is performed in the form of an interrupt to another arithmetic device . The other processing can be executed until the requested computation is completed in the second computing device , and the computation result of the requested computation processing is held in the shared memory and the shared general-purpose register. End information is set. Therefore, the first arithmetic unit only needs to confirm the arithmetic processing end information and read the arithmetic result when necessary, and the second arithmetic unit also processes the requested processing within an interrupt, and requests the requested arithmetic operation. At the end of the process, it is only necessary to set the calculation result and the calculation process end information and return to the main calculation process, so that the calculation process that requires a complicated process that conventionally required a plurality of calculation devices can be efficiently performed, It can be realized with an inexpensive system. In other words, efficient software can be created with efficient hardware.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  As an embodiment of the complex arithmetic processing device of the present invention, an independent 16-bit arithmetic processing device (hereinafter referred to as a microcontroller) and a 16-bit data width / 32-bit instruction code width characterized by product-sum operation are provided. A complex arithmetic processing device including an arithmetic processing device (hereinafter referred to as a digital signal processor) will be described.

  FIG. 1 shows a 16-bit microcontroller having a shared memory (shared instruction memory and shared data memory) and a shared general-purpose register and a digital signal processor having a 16-bit data width / 32-bit instruction code width according to an embodiment of the present invention. It is a block diagram of the compound arithmetic processing apparatus consisting of.

  In FIG. 1, reference numeral 101 denotes a shared instruction memory for a digital signal processor and a microcontroller, which has a plurality of ports.

  Reference numeral 102 denotes a shared data memory for the digital signal processor and the microcontroller, which has a plurality of ports.

  Reference numeral 103 denotes a local data memory that can be accessed only by the digital signal processor.

  Reference numeral 104 denotes a shared instruction memory pointer for the microcontroller.

  Reference numeral 105 denotes a shared instruction memory pointer for the digital signal processor.

  Reference numeral 106 denotes a shared data memory pointer for the microcontroller.

  Reference numeral 107 denotes a shared data memory pointer for the digital signal processor.

  Reference numeral 108 denotes a local data memory pointer for the digital signal processor.

  Reference numeral 109 denotes a general-purpose register shared by the digital signal processor and the microcontroller, and has a plurality of ports.

  Reference numeral 110 denotes a processing unit for the microcontroller.

  Reference numeral 111 denotes an arithmetic processing unit for a digital signal processor.

  Reference numeral 112 denotes a multiplier for the digital signal processor.

  Reference numerals 113, 114 and 115 denote shared external input / output units (shared peripheral input / output units) for the microcontroller and the digital signal processor.

  Reference numeral 116 denotes an instruction code address bus (shared instruction memory address bus) for the microcontroller.

  Reference numeral 117 denotes an instruction code address bus (shared instruction memory address bus) for the digital signal processor.

  Reference numeral 118 denotes an instruction code data bus (shared instruction memory data bus) for the microcontroller.

  Reference numeral 119 denotes an instruction code data bus (shared instruction memory data bus) for the digital signal processor.

  Reference numeral 120 denotes a shared data memory data bus for the microcontroller.

  Reference numeral 121 denotes a shared data memory data bus for the digital signal processor.

  Reference numeral 122 denotes a local data memory data bus for the digital signal processor.

  Reference numeral 123 denotes an instruction decoding unit for the microcontroller.

  An instruction decoding unit 124 for the digital signal processor.

  FIG. 2 shows the structure of the shared instruction memory 101. In FIG. 2, 201 and 202 are instruction memory areas having a 16-bit × N two-sided structure and having a plurality of ports.

  Reference numeral 203 denotes an instruction memory management unit for the microcontroller (which constitutes access means in the claims).

  Reference numeral 204 denotes an instruction memory management unit for digital signal processors (which constitutes access means in the claims).

  Reference numeral 205 denotes an instruction memory maximum address value setting register for the microcontroller.

  Reference numeral 206 denotes an instruction memory minimum address value setting register for the digital signal processor.

  A comparison unit 207 compares the current address value for the microcontroller with the setting value of the instruction memory maximum address value setting register 205.

  A comparison unit 208 compares the current address value for the digital signal processor with the set value of the instruction memory minimum address value setting register 206.

  Reference numeral 209 denotes an instruction code address bus for the microcontroller.

  210 is an instruction code address bus for the digital signal processor.

  211 is an instruction code data bus for the microcontroller.

  Reference numeral 212 denotes an instruction code data bus for the digital signal processor.

  FIG. 3 shows the structure of the rewritable shared data memory 102. In FIG. 3, 301, 302, 303, and 304 are rewritable data memory areas, each of which is a segment unit area of 16 bits × N (N is preferably a power of 2), and has a multifaceted structure. Has a port.

  Reference numeral 305 denotes a data memory management unit for the microcontroller (which constitutes access means in the claims).

  Reference numeral 306 denotes a data memory management unit for digital signal processors (which constitutes access means in claims).

  Reference numeral 307 denotes a shared data memory segment unit selection value setting register.

  A comparison unit 308 compares the current address value for the microcontroller with the segment selection value of the shared data memory segment unit selection value setting register 307.

  A comparison unit 309 compares the current address value for the digital signal processor with the segment selection value of the shared data memory segment unit selection value setting register 307.

  Reference numeral 310 denotes a shared data memory access status flag register (which constitutes access status notification means in the claims).

  Reference numeral 311 denotes a shared data memory data bus for the microcontroller.

  Reference numeral 312 denotes a shared data memory data bus for the digital signal processor.

  Reference numeral 313 denotes a shared data memory address bus for the microcontroller.

  Reference numeral 314 denotes a shared data memory address bus for the digital signal processor.

  Reference numeral 315 denotes a shared data memory write signal for the microcontroller.

  Reference numeral 316 denotes a shared data memory read signal for the microcontroller.

  Reference numeral 317 denotes a shared data memory write signal for the digital signal processor.

  Reference numeral 318 denotes a shared data memory read signal for the digital signal processor.

  FIG. 4 shows the structure of the shared general purpose register 109. In FIG. 4, 401, 402, and 403 to 40N are general-purpose registers, each of which has a configuration of 16 bits × N (N is preferably a power of 2), and has a plurality of ports.

  Reference numeral 410 denotes a register selection unit for the microcontroller.

  Reference numeral 411 denotes a register selection unit for a digital signal processor.

  Reference numeral 412 denotes an access permission / prohibition information setting register of the shared general-purpose register 109 (which constitutes access permission / prohibition setting means in the claims). Each of the general-purpose registers 401, 402, 403 to 40N is a microcontroller or a digital signal processor. It is a register that sets whether or not it can be accessed from.

  Reference numeral 413 denotes a shared data memory data bus for the microcontroller.

  Reference numeral 414 denotes a shared data memory data bus for the digital signal processor.

  Reference numeral 415 denotes a shared data memory address bus for the microcontroller.

  Reference numeral 418 denotes a shared data memory address bus for the digital signal processor.

  Reference numeral 416 denotes a shared data memory write signal for the microcontroller.

  Reference numeral 417 denotes a shared data memory read signal for the microcontroller.

  Reference numeral 419 denotes a shared data memory write signal for the digital signal processor.

  Reference numeral 420 denotes a shared data memory read signal for a digital signal processor.

  A flag register 421 indicates whether or not the corresponding general-purpose registers 401, 402, and 403 to 40N are accessed. FIG. 5 shows the configuration of the shared external input / output units 113 to 115.

  In FIG. 5, reference numeral 501 denotes an output data buffer.

  Reference numeral 502 denotes an input data buffer.

  Reference numeral 503 denotes an external input / output control unit (which constitutes access means in the claims).

  A state holding unit 504 indicates the state of the shared external input / output units 113 to 115.

  Reference numeral 505 denotes an access permission / prohibition information setting register for setting access permission / prohibition information from the microcontrollers and digital signal processors of the shared external input / output units 113 to 115 (which constitutes access permission / prohibition setting means in the claims). It is.

  Reference numeral 506 denotes an interrupt signal generator (which constitutes an interrupt signal generator in the claims) that generates an interrupt to the arithmetic processing unit according to the state of the shared external input / output units 113 to 115.

  Reference numeral 507 denotes an external input / output terminal.

  Reference numeral 510 denotes a shared data memory data bus of the microcontroller.

  Reference numeral 511 denotes a shared data memory data bus of the digital signal processor.

  512 is a shared external input / output interrupt signal for the microcontroller.

  Reference numeral 513 denotes a shared external input / output unit interrupt signal for the digital signal processor.

  Reference numeral 514 denotes an output data bus from the output data buffer 501 to the external input / output terminal 507.

  Reference numeral 515 denotes an input data bus from the external input / output terminal 507 to the input data buffer 502.

  Reference numeral 516 denotes a shared external input / output unit selection signal from the microcontroller.

  Reference numeral 517 denotes a shared external input / output selection signal from the digital signal processor.

  Reference numeral 518 denotes an external input / output signal.

  The operation of the microcontroller and digital signal processor will be described in detail below.

Microcontroller:
First, the address of the instruction of the microcontroller enters the instruction memory management unit 203 in FIG. 2 from the shared instruction memory pointer 104 in FIG. 1 through the instruction code address bus 116 and the instruction code address bus 209 in FIG. In the instruction memory management unit 203, the address input from the instruction code address bus 209 is compared with the instruction memory maximum address setting value held in the instruction memory maximum address value setting register 205. Are output as the addresses of the instruction memory areas 201 and 202 of the shared instruction memo 101. If it is determined that the address exceeds the set value, it is an instruction memory area allocated to the digital signal processor, which is determined to be a program error and is converted to an address for executing the abnormal termination process. In the instruction memory areas 201 and 202, the instruction code corresponding to the address is output as instruction code data to the instruction code data bus 211, and enters the instruction decoding unit 123 through the instruction code data bus 118 of FIG. The instruction decoding unit 123 decodes the instruction and outputs the instruction to the corresponding part so as to execute processing corresponding to the instruction.

  When viewed from the microcontroller side, the instruction memory areas 201 and 202 have an even word structure in the instruction memory area 201 and an odd word structure in the instruction memory area 202, and the least significant bit of the instruction code address bus 209 is the instruction memory area. This is a selection bit for the area 201/202. If the address output to the instruction code address bus 209 is an even number, the corresponding instruction code data is output from the instruction memory area 201 to the instruction code data bus 211, and output on the instruction code data bus 211 side of the instruction memory area 202 Becomes a high impedance state. On the other hand, when the address output to the instruction code address bus 209 is an odd number, the output on the instruction code data bus 211 side of the instruction memory area 201 is in a high impedance state, and the corresponding instruction code data from the instruction memory area 202 is It is output to the instruction code data bus 211.

  Next, when the microcontroller accesses the shared data memory 102, the address passes through the shared data memory pointer 106 in FIG. 1 and the shared data memory address bus 313 in FIG. 3, and enters the data memory management unit 305 in FIG. . In the data memory management unit 305, the address input from the shared data memory address bus 313 and the setting value held in the shared data memory segment unit selection value setting register 307 are compared by the comparison unit 308 to access the microcontroller. If the address is permitted, the address is directly output as the address of the data memory areas 301 to 304 of the shared data memory 102. If the address is not permitted, the address to the data memory areas 301 to 304 of the shared data memory 102 is output. Stop the output of. At this time, it is also possible to notify with a flag or the like that an attempt was made to access the address of the prohibited segment. When the address of the permitted segment in the data memory area 301 to 304 of the shared data memory 102 is written and accessed, the segment of the shared data memory access status flag register 310 is notified in order to notify that the content of the segment has been changed. Set the corresponding flag. By making it possible to read this flag also from the digital signal processor, it is possible to control the shared data on the shared data memory 102 and the processing of the data.

  That is, by making it possible to read the access status flag also from the digital signal processor, it is possible to know the segment on which the rewrite on the shared data memory has been executed. Further, the microcontroller can change the value of the segment unit selection value setting register so as to permit the digital signal processor to access the segment of the shared data memory to which access is permitted. With these operations, shared data on the shared data memory and data processing can be controlled (refer to FIG. 6 for the permission / prohibition sequence of the data transfer access).

  For the data at the address permitted to be accessed, each of the writing process and the reading process is appropriately executed according to the data memory write signal 315 and the data memory read signal 316.

  Access to the shared general-purpose register 109 of the microcontroller is the same as that of the shared data memory 102, and a register designation signal is input to the register selection unit 410 through the shared data memory address bus 415 of FIG. 4. In the register selection unit 410, the access permission / prohibition information setting register 412 indicates whether or not the general-purpose registers 401 to 40N specified by the register specification signal passing through the shared data memory address bus 415 permit access from the microcontroller. If the access is possible, an access signal is output to the designated general-purpose registers 401 to 40N. If the general-purpose registers 401 to 40N are not permitted, the output of the access signal to the designated general-purpose registers 401 to 40N is stopped. At this time, it is also possible to notify with a flag or the like that an attempt was made to access the prohibited general-purpose register. The general-purpose registers 401 to 40N that are permitted to access are appropriately subjected to write processing and read processing in accordance with the data memory write signal 416 and the data memory read signal 417.

Digital signal processor:
First, the instruction of the digital signal processor has its address from the shared instruction memory pointer 105 in FIG. 1 through the instruction code address bus 117 and the instruction code address bus 210 in FIG. 2, and enters the instruction memory management unit 204 in FIG. . In the instruction memory management unit 204, the address input from the instruction code address bus 210 is compared with the instruction memory minimum address setting value held in the instruction memory minimum address value setting register 206. Are output as the addresses of the instruction memory areas 201 and 202 of the shared instruction memory 101. When it is determined that the address is equal to or less than the set value, it is an instruction area assigned to the microcontroller, which is determined to be a program error and is converted to an address for executing an abnormal termination process. In the instruction memories 201 and 202, the instruction code corresponding to the address is output to the instruction code data bus 212 as instruction code data, and enters the instruction decoding unit 124 through the instruction code data bus 119 of FIG. The instruction decoding unit 124 decodes the instruction and outputs the instruction to the corresponding part so as to execute processing corresponding to the instruction.

  When viewed from the digital signal processor side, the instruction memory areas 201 and 202 have a lower word structure in the instruction memory area 201 and an upper word structure in the instruction memory area 202, and correspond to the address data value of the instruction code address bus 209. The instruction code data, which is 16 bits from the instruction memory area 201 and 16 bits from the instruction memory area 202, is output to the instruction code data bus 212.

  Next, as for the access to the shared data memory 102 of the digital signal processor, the address passes through the shared data memory pointer 107 in FIG. 1 and the shared data memory address bus 314 in FIG. The data memory management unit 306 is entered. In the data memory management unit 306, the comparison unit 309 compares the address input from the shared data memory address bus 314 with the set value held in the shared data memory segment unit selection value setting register 307, and the digital signal processor If the access is permitted, the address is output as it is as the address of the data memory areas 301 to 304 of the data memory 102. If the address is not permitted, the output of the address to the shared data memory 102 is stopped. At this time, it is also possible to notify with a flag or the like that an attempt was made to access the address of the prohibited segment. When the address of the permitted segment in the data memory area 301 to 304 of the shared data memory 102 is written and accessed, the segment of the shared data memory access status flag register 310 is notified to notify that the content of the segment has been changed. Set the corresponding flag. By making it possible to read this flag from the microcontroller 4 as well, shared data on the shared data memory 102 and data processing can be controlled.

  That is, by making it possible to read the access status flag also from the digital signal processor, it is possible to know the segment on which the rewrite on the shared data memory has been executed. Further, the microcontroller can change the value of the segment unit selection value setting register so as to permit the digital signal processor to access the segment of the shared data memory to which access is permitted. With these operations, shared data on the shared data memory and data processing can be controlled (refer to FIG. 6 for the permission / prohibition sequence of the data transfer access).

  The data at the address for which access is permitted is subjected to a write process and a read process in accordance with the data memory write signal 317 and the data memory read signal 318.

  In the access to the shared general-purpose register 109 of the digital signal processor, a register designation signal is input to the register selection unit 411 through the shared data memory address bus 418 of FIG. In the register selection unit 411, whether or not the register specified by the register specification signal 418 that has passed through the shared data memory address bus 418 permits access from the digital signal processor, the contents of the access permission / prohibition information setting register 412 And if it is accessible, an access signal is output to the designated general-purpose registers 401 to 40N. If the general-purpose registers 401 to 40N are not permitted, the output of the access signal to the designated general-purpose registers 401 to 40N is stopped. At this time, it is also possible to notify with a flag or the like that an attempt was made to access the prohibited general-purpose register. The general-purpose registers 401 to 40N that are permitted to access are appropriately executed in accordance with the data memory write signal 418 and the data memory read signal 419, respectively.

Access to shared external input / output units 113-115:
Access to the shared external input / output units 113 to 115 is the same access as the shared data memory 102 and the shared general-purpose register 109.

  When the microcontroller accesses the shared external input / output units 113 to 115, the shared external input / output unit selection signal 516 in FIG. 5 is input to the shared external input / output unit control unit 503 from the microcontroller. The shared external input / output unit control unit 503 confirms the contents of the access permission / prohibition information setting register 505 in the shared external input / output units 113 to 115. If the access of the microcontroller is permitted, the shared external input / output unit control unit 503 shares the microcontroller. Access between the data memory data bus 510, the output data buffer 501, and the input data buffer 502 is executed. At the same time, the status holding unit 504 that holds the statuses of the shared external input / output units 113 to 115 is changed according to the result. When the state change of the shared external input / output units 113 to 115 becomes an interrupt factor, the interrupt signal generation unit 506 generates a shared external input / output unit interrupt signal 512 for the microcontroller. When access of the microcontroller is prohibited, access to the actual shared external input / output units 113 to 115 is not executed. However, a flag for notifying that prohibited access has been executed is set.

  When the digital signal processor accesses the shared external input / output units 113 to 115, the shared external input / output unit selection signal 517 of FIG. 5 is input to the shared external input / output unit control unit 503 from the digital signal processor. The shared external input / output unit control unit 503 confirms the contents of the access permission / prohibition information setting register 505 in the shared external input / output units 113 to 115, and if access to the digital signal processor is permitted, the digital signal processor The shared data memory data bus 511, the output data buffer 501, and the input data buffer 502 are accessed. At the same time, the status holding unit 504 that holds the statuses of the shared external input / output units 113 to 115 is changed according to the result. When the state change of the shared external input / output units 113 to 115 becomes an interrupt factor, the interrupt signal generation unit 506 generates a shared external input / output unit interrupt signal 513 for the digital signal processor. When access of the digital signal processor is prohibited, access to the actual shared external input / output units 113 to 115 is not executed. However, a flag for notifying that prohibited access has been executed is set.

Processing request interrupt:
FIG. 6 shows a sequence in the case where a request interrupt for arithmetic processing is executed from the microcontroller to the digital signal processor.

  601: Operation processing request side, in this example, the microcontroller sets the requested processing contents and processing data in the shared general-purpose register 109 and the shared data memory 102.

  In this example, in the shared general-purpose register 109 in FIG. 1, the operation processing number “k” for which processing is requested is stored in the general-purpose register 401 in FIG. 4, and the start address “M” of the data memory area to which the operation processing is to be executed is illustrated in FIG. The number of data “N” is set in the general-purpose register 402 in the general-purpose register 403 in FIG. 4, and “N” is stored in the rewritable data memory area 302 in FIG. Pieces of data are set.

  602: After setting these data, the operation requestee accesses the set shared general-purpose register 109 (general-purpose registers 401 to 403 in FIG. 4) and shared data memory 102 (rewritable data memory area 302 in FIG. 3). The contents of the shared data memory segment unit selection value setting register 307 in FIG. 3 and the access permission / prohibition information setting register 412 in FIG. 4 are changed so as to be possible.

  603: The calculation processing request side (microcontroller) generates an interrupt to the calculation processing request side (digital signal processor) (corresponding to the interrupt means in the claims).

  604; Thereafter, the calculation processing requesting side (microcontroller) executes another processing.

  605: The operation processing requesting side (digital signal processor) accepts an operation processing request interrupt while the main processing is being executed.

  606: An interrupt is executed. At the beginning of the interrupt process, the contents of the general-purpose registers 401, 402, and 403 of the shared general-purpose register 109 are confirmed, and the requested arithmetic process is executed using the data in the rewritable data memory area 302 of the shared data memory 102. .

  In this example, the processing of the arithmetic processing number “k” of the general-purpose register 401 in FIG. 4 is executed using “N” data from the address “M” in the rewritable data memory area 302 in FIG. Data is written after the address “M” in the rewritable data memory area 302 of FIG.

  607: A code notifying the end of the calculation is set in the general-purpose register 401 in FIG.

  608; the shared data memory segment of FIG. 3 so that the operation requesting side can access the used shared general register 109 (general registers 401 to 403 of FIG. 4) and the shared data memory 102 (data memory area 302 of FIG. 3). The contents of the unit selection value setting register 307 and the access permission / prohibition information setting register 412 in FIG. 4 are changed.

  609: End the interrupt.

  610: The computation processing request side executes the original main processing.

  611: The calculation processing requester polls the processing end code of the general-purpose register 401 in FIG. 4 (corresponding to the calculation processing end information setting means in the claims).

  612: After confirming that the requested arithmetic processing is completed, the process proceeds to the next processing. It is also possible for the digital signal processor to request computation processing and interrupt the microcontroller.

  In the above description, one of the most preferred embodiments has been described. However, the present invention is not limited to this, and any one of the memory, the general-purpose register, and the external input / output unit is not shared but is provided separately. Can be given as

  The complex arithmetic processing apparatus according to the present invention can realize arithmetic processing requiring complicated processing, which conventionally required a plurality of arithmetic processing units, with an efficient and inexpensive system. In other words, it has the effect that it is possible to create efficient software with efficient hardware, such as a complex arithmetic processing device that is executed in order, with instructions to the complex arithmetic processing device being derived by a variable program Useful.

It is a block diagram which shows the structure of the compound arithmetic processing apparatus of one Example of this invention. FIG. 2 is a block diagram showing a specific configuration of a shared instruction memory in FIG. 1. It is a block diagram which shows the specific structure of the shared data memory in FIG. It is a block diagram which shows the specific structure of the shared general purpose register in FIG. FIG. 2 is a block diagram illustrating a specific configuration of a shared external input / output unit in FIG. 1. It is the schematic which shows the arithmetic processing request interruption sequence in the compound arithmetic processing apparatus of FIG.

Explanation of symbols

101 Shared Instruction Memory 102 Shared Data Memory 103 Local Data Memory 104 Shared Instruction Memory Pointer 105 Shared Instruction Memory Pointer 106 Shared Data Memory Pointer 107 Shared Data Memory Pointer 108 Local Data Memory Pointer 109 Shared General Purpose Register 110 Operation Processing Unit 111 Operation Processing Unit 112 Multiplier 113 Shared external input / output unit 114 Shared external input / output unit 115 Shared external input / output unit 116 Instruction code address bus 117 Instruction code address bus 118 Instruction code data bus 119 Instruction code data bus 120 Shared data memory data bus 121 Shared data memory Data bus 122 Local data memory Data bus 123 Instruction decoding unit 124 Instruction decoding unit 201 Instruction memory area 202 Instruction memory area 203 Instruction memory tube Unit 204 Instruction memory management unit 205 Instruction memory maximum address value setting register 206 Instruction memory minimum address value setting register 207 Comparison unit 208 Comparison unit 209 Instruction code address bus 210 Instruction code address bus 211 Instruction code data bus 212 Instruction code data bus 301 Data Memory area 302 Data memory area 303 Data memory area 304 Data memory area 305 Data memory management section 306 Data memory management section 307 Shared data memory segment unit selection value setting register 308 Comparison section 309 Comparison section 310 Shared data memory access status flag register 311 Shared Data memory data bus 312 Shared data memory data bus 313 Shared data memory address bus 314 Shared data memory address bus 315 Shared data Memory write signal 316 Shared data memory read signal 317 Shared data memory write signal 318 Shared data memory read signal 401 General purpose register 402 General purpose register 403 General purpose register 40N General purpose register 410 Register selection unit 411 Register selection unit 412 Access permission / prohibition information setting register 413 Shared data memory data bus 414 Shared data memory data bus 415 Shared data memory address bus 416 Shared data memory write signal 417 Shared data memory read signal 418 Shared data memory address bus 419 Shared data memory write signal 420 Shared data memory read signal 421 Flag register 501 Output data buffer 502 Input data buffer 503 External input / output control unit 504 Status holding unit 50 Access permission / prohibition information setting register 506 Interrupt signal generator 507 External input / output terminal 510 Shared data memory data bus 511 Shared data memory data bus 512 Shared external input / output interrupt signal 513 Shared external input / output interrupt signal 514 Output data bus 515 Input data bus 516 Shared external input / output unit selection signal 517 Shared external input / output unit selection signal 518 External input / output signal

Claims (1)

First and second independent arithmetic devices having different characteristics of arithmetic processing, a shared memory having two ports and connected to the first and second arithmetic devices, and the first having two ports A shared general-purpose register connected to the second arithmetic unit; first and second access means for accessing the shared memory and the shared general-purpose register from the first and second arithmetic units; An interrupt unit provided in one arithmetic unit to generate an interrupt to the second arithmetic unit; and an end of arithmetic processing by the interrupt provided in the second arithmetic unit to the first arithmetic unit. Computation processing end setting means for notifying,
The first arithmetic unit performs arithmetic processing on the second arithmetic unit by the interrupt means when an operation suitable for processing in the second arithmetic unit occurs in the course of arithmetic processing. The request is generated as an interrupt, and the data necessary for the arithmetic processing is stored as an argument in the shared general-purpose register and the shared memory.
The second arithmetic unit executes the requested arithmetic processing using the argument, stores the operation result data as a return number in the shared general-purpose register and the shared memory, and the arithmetic processing end setting means Set the calculation processing end information ,
The shared memory has a rewritable area, and access permission / prohibition for setting access permission / prohibition information from the first and second arithmetic units for each predetermined range of the shared memory and the shared general-purpose register, respectively. Providing an information setting means, providing an access status setting means for transmitting the access status from the first and second arithmetic devices to the second and first arithmetic devices for each predetermined range of the shared memory;
The first and second access means access the shared memory and the shared general-purpose register only in a range where access is permitted while referring to the setting contents of the access permission / prohibition information setting means, Access to the rewritable area of the shared memory while referring to the setting contents of the access status setting means,
The first arithmetic unit has completed the setting of the argument when an argument is set in the shared general-purpose register and the shared memory when the second arithmetic unit is requested to perform an operation. Set by the access status setting means, and the permission / prohibition information of the area holding the argument in the shared general-purpose register and the shared memory is reversed by the access permission / prohibition information setting means,
When the second arithmetic unit completes the requested arithmetic processing, the access status setting means indicates that the return number has been set when the return number is set in the shared general-purpose register and the shared memory. A combined arithmetic processing apparatus characterized in that the permission / prohibition information of the area holding the return number in the shared general-purpose register and the shared memory is reversed by the access permission / prohibition information setting means .

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