JPH0375850A - Memory access processor - Google Patents

Abstract

PURPOSE:To prevent the degradation of performance at the time of the overlapping of a request from a requesting source with the write-in of an M-bit by holding an address for registering the M-bit of an address array, and registering this M-bit in the case of no processing to read out the address array due to the request from the requesting source. CONSTITUTION:An address storage means 304 is provided, and when the write-in of the M-bit and the read-out of the address array for the index of the address array 302 due to the processing of the requesting source are overlapped with each other, the registering address of the M-bit is held temporarily in the address storage means 304. Then, in the case of no read-out of the address array for the index of the address array 302 due to the processing of the requesting source, the registration of M-bit is executed by an address array write-in control means 305. Thus, the processing of the requesting source is not stopped, and the performance can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access processing device internally equipped with a swap type cache memory.

[Conventional technology]

Conventionally, in this type of memory access processing device equipped with an internal swap-type cache memory, all memory access processing is performed within the cache, so even in response to a write specification from a request source, writing is performed only within the cache. Do not write to the main memory even if it is done. Therefore, in a normal state, the contents of the cache and the contents of the main storage device do not match, so when the contents of the cache are rewritten by a new access, the contents of the cache are written back to the main storage device to ensure consistency. Information indicating whether the contents of the cache have been rewritten at this time,
That is, it has an M bit and is controlled to write to the main memory only when this indicates rewriting, so as not to issue unnecessary memory accesses. Therefore, if the contents of the address corresponding to a write request from the request source exist in the cache, the M bit is checked to see if it indicates rewriting, and if it does not indicate rewriting, a new one is set to indicate rewriting. (This process is called M-bit registration)
.

In such processing, successive memory access requests from input/output devices or arithmetic processing units are passed through a series of registers and processed continuously, and the processing JTp is not completed within one pipeline flow. In some cases, it is impossible to process a series of pipelines once in a processing device with a cyclical vibe line configuration that returns to the beginning of the pipeline and processes again in the same pipeline flow. - Back to the beginning of the vibe line, evening, lp
Writing is performed by processing l[1. At this time, in the conventional device, even if there is an access request from the request source, the writing of the M bit is given priority, and control is performed so as not to wait for the request source to process.

[Problem that the invention seeks to solve]

The conventional method described above has the disadvantage that since priority is given to M-hit writes, when a request from a request source overlaps with a write from M-hit, the request source's processing is forced to wait, resulting in decreased performance. There is.

(Means for Solving the Problems) The present invention provides a data array that is connected to an input/output device or an arithmetic processing unit and a main storage device and holds a copy of a part of the contents of the main storage device; A memory bag (has an address array that holds information indicating which part of the 4 characters corresponds to the memory bag, and M hits indicating whether the information has been rewritten), and has an address array that stores information indicating which part of the If a memory access request can be processed within the data array, the swap-based cache is modified so that the request is processed only within the data array, regardless of whether it is a write or read. Consecutive memory access requests are rotated through trace registers and processed continuously, and if the processing is not completed within one pipeline flow, the process returns to the beginning of the pipeline and repeats the same pipeline again. In a memory access processing device having a cyclical pipeline configuration that performs processing in the flow of !5, an address memory that holds addresses for registering M hits of an address array.

and address array write control means for registering the M bits when there is no processing to read the address array according to a request from a request source.

(Function) The M bit is registered only when there is no processing from the requesting source, and if there is processing from the requesting source, the address is sent to the address storage means and held there, and the address is stored there. Process reading of the address array with priority. Thereafter, the address array write control means constantly monitors whether there is any reading of the address array by processing from the request source, and registers M bits in the address array when there is no reading of the address array.

In this way, reading of the address array for indexing the address array by the requesting process can be prioritized and processed without waiting.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a memory access processing device of the present invention.

Request sources 101 to 103 such as input/output devices and arithmetic processing units
"Circuit 2 receives each memory access request from
01-203 are accepted. One of the accepted requests is selected by the selection means 204 and processed. The address of the accepted request source is stored in address register 3.
01 and its subscript 7 traces address array 3.
The content of 02 is read out and compared with the upper address of the address register 301 by the comparing means 303 to check whether the content of the address requested by the request source exists in the corresponding data array 403 (such a series of operations). the address array index and come true). As a result of such indexing of the address array, if the requested data exists in the data array 403 (this case is called a hit), the contents of the address register 301 are transferred to the address register 403.
Read or write processing is performed within the data array 403 according to the request content of the request source. Furthermore, if the result of indexing the address array is that it does not exist in the data array 403 (this case is called a miss), the main memory 601 is accessed and the necessary contents are stored in the main memory bag Q''!
Read from f 601, and if the request is a REIT, send the necessary data to the request source and write to the data array 403 at the same time, and if there is a write, write data and the main memory 601
After combining the read data, data array 403 is written. At this time, M bits are simultaneously read from the address array 302, and it is checked whether the contents of the corresponding data array 403 have been rewritten at 1°. This result is also i! (If it indicates that the swap address register 402 has been swapped, the contents of the address array 302 or the main memory 6
01 address selection means 404 (7) is sent to the main memory device fil+, and the contents of the data array 403 are written before reading the main memory device 601 (this operation is called a swap error). ).

Next, a method of registering M bits in address array 302 will be described.

If the request from the request source is a write and the result of indexing the address array 302 is a hit, M hits are read from the address array 302 at the same time. As a result, if the M hit is 0°, indicating that it has not been changed many times, then in the case of the conventional device, the address register;
)ol of the request source address in address register 4.
01, the address register 501, and returns to the address register 301 again.

After this, M bits are registered at the address indicated by address register :)01. For this reason, even if there is a request from a request source at the same time, priority is given to registering the M bit, so the process of the request source is forced to wait. In the case of this embodiment, the address is sent to the address register 301 only when there is no processing from the request source after the address is sent to the address register 501. Pg3 is executed, and if there is a process by the request source, the address is sent to the address storage means (04) and held there, and processing is given priority to reading the address array 302 by the process by the request source. Thereafter, the address array write control means 305 constantly monitors whether or not the address array 102 is read by processing from the request source, and when the address array 302 is not read, the address array 302 is
Performs M-bit data recording.

In this way, reading of the address array for indexing the address array by the requesting process can be prioritized and processed without waiting.

〔Effect of the invention〕

As explained above, the present invention has an address storage means, and when writing of M bits and reading of the address array for indexing the address array by request source processing overlap, the registered addresses of M bits are stored in the address storage means. By configuring the address array write control means to register the M bit when there is no reading of the address array for indexing of the address array by the process of the request source. This has the effect of improving performance without stopping the original processing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a memory access processing device of the present invention. 101-103...Request source 201-203...Reception 1i-1 circuit 20/l...
...Selection f-stage 0 Address register Address array comparison means Address storage means Address array write control means Selection means Atres register Swap address register Data array selection means Address register Main memory

Claims (1)

[Claims] A data array that is connected to an input/output device or an arithmetic processing unit and a main memory and holds a copy of a part of the contents of the main memory; It has an address array that holds information indicating whether the information corresponds to the data array and M bits indicating whether the information has been rewritten. It has a swap-type cache that processes consecutive memory access requests from input/output devices or arithmetic processing units only within the data array, regardless of whether the request is read or written, if it can be processed. A cyclic process in which processing is performed continuously in rotation, and if the processing is not completed in one pipeline flow, it returns to the beginning of the pipeline and performs processing again in the same pipeline flow. A memory access processing device having a pipeline configuration includes an address storage means for holding an address for registering the M bits of the address array, and an address storage means for storing the address for registering the M bits of the address array when there is no processing to read the address array according to a request from a request source. 1. A memory access processing device comprising: address array write control means for performing registration.