JPS58109952A - Storage access processor - Google Patents

Abstract

PURPOSE:To attain efficient storage access processing, by performing revision processing of a control memory in parallel with the write of buffer, only when the buffer collating information in the control memory is required for revision. CONSTITUTION:When a partial write instruction is received in an interface register 4 of a data processor CPU0, a control memory 20 checks the correspondence of data of collating information between a buffer of each CPU and a buffer 14 of a storage controller is checked at the control memory 20. When a BI logical circuit 24 detects ''1'' at an area other than the CPU0, and an instruction BIRQ making the data ineffective is transmitted to the buffer of the CPU corresponding to ''1''. Through the instruction from the circuit 24, a reapplication logical circuit 25 sets a write signal to a buffer 14 together with a pipeline reapplication request for the revision of the memory 20 to a pipeline constituent 13. This request passes through a priority control circuit 6 from the element 13, performs write control for the buffer 14 and revises the memory 20 via pipeline constituents 7, 8.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a storage access processing device in a data processing system in which buffers are configured at two levels: within a data processing device and within a storage control device. In particular, the present invention relates to a storage access processing device that efficiently controls rewriting of a control memory provided for aligning the contents of these buffers when updating stored data.

(2) Background of the technology In a data processing system in which multiple data processing devices share a storage device, in order to reduce the number of accesses to the storage device and increase processing speed, each data processing device has a
In the intermediate storage controller and K.

A two-level buffer is provided, and frequently used data is stored in these buffers so that they can be read and written at high speed.

FIG. 1 shows an example of the configuration of such a data processing system. In the figure, 1.1' indicates n+1 data processing devices CP Uo to CPUn, each of which has a buffer B.
81 is shown. 2 is buffer BS, 2
This is a storage control unit MCU having a pipeline control structure including a control memory BIMFIM and a control memory BIMFIM. 3.3' is m
+1 storage devices M S Uo to M 8 U are shown.

Storage device [M2O3 to M 8 Um are storage control device M
Data processing devices CP Uo to CPU via CU
[Therefore, it is shared.] Also, the buffer B82 is the storage device M.
8 U. It has a part of M 8 Unl to M 8 Unl, and is shared by the data processing devices CP Uo to CPU Yu.

The control memory BIMEM in the MCU holds buffer contrast information indicating in which CPU's buffer BSI a copy of the data in buffer B82 resides.

Figure 2 (a) t (b) shows B82 and BIMFi
It is a figure which illustrated the structure and correspondence of M. Figure 2 (1) shows BH3, 64 bytes, XY8ET of X association level.
is divided into 4 BANKs of 16 bytes each. Figure 2(b) shows BIMEM, the configuration is 88
It consists of eight n+1-bit X-associative level XYSETs corresponding to about 2KPk and corresponding to each CPUK. B82
The hatched part of BIMffM corresponds to the CPU that holds each 64-byte data of BH3 in BSl,
The corresponding CPUK of the corresponding buffer contrast information in BIMBM
It is displayed by setting the corresponding bit position K"l".

Figure 3 shows each Bi1 for certain 64-byte data.
2 and the corresponding buffer contrast information display of BIMEM is shown.

When any CPU accesses certain data in the MSU, that data is held in B81 in the accessed CPU and B82 in the MCU, and
The situation will be recorded by BIMEMK.

Also, when any CPU performs data update processing, that is, executes a store instruction, the contents of BH3 are changed, so if old data corresponding to BS1 in the other CPU is retained, requires processing to disable it. At this time, the MCU
The contents of the BM are read and an invalidation command (BIRQ) is sent to the relevant CPU. Furthermore, in this case, the MCU is B
It is necessary to rewrite the buffer comparison information in the IBMM to correspond to the situation after the invalidation process.

However, if the information read from HIMEM indicates that no copy of the data to be updated exists on the BS1 of any other CPU, the B I R
A logic operation is required to prevent Q from being sent and BIMEM from being rewritten.

In the conventional storage control unit MCU, the above-mentioned control memory BIMF! Special pipeline cycles are required to perform MK-associated update processing. Therefore, in the case of data processing using a large number of store instructions, this causes a reduction in processing efficiency, which is a problem.

(3) Purpose of the Invention The present invention provides a storage control device that can execute control memory operations with almost no reduction in efficiency even when a large number of store instructions are executed in succession. The purpose of the present invention is to provide an access processing device.

(4) Structure of the Invention The present invention is a storage control device that automatically generates a big line re-input request internally and starts the pipeline only when it is necessary to update buffer comparison information in the control memory. However, the control memory update process is performed in parallel with the buffer write operation, thereby improving the efficiency of the memory access process.

As a configuration for this purpose, the present invention provides a plurality of data processing apparatuses having a first buffer used only by the own apparatus, a second buffer that can be accessed by all of the plurality of data processing apparatuses, and the second buffer and the above-mentioned WLl buffer. In a data processing system, the data processing system includes a storage control device that has a control memory that indicates correspondence between the contents of the data and is subjected to bigline control, and a storage device, a circuit that detects the necessity of rewriting the contents of the control memory, and a cough detection circuit. and a request re-input circuit controlled by the controller, and when a store instruction is given, first inputs a request to perform convolution on the second buffer to the storage control snowmaking pipeline;
When the detection circuit detects the need to rewrite the contents of the control memory, it controls the request re-input circuit to re-input the request re-input circuit (for rewriting the contents of the control memory) into the pipeline. do.

(5) Embodiment of the invention FIG. 4 is a block diagram of an embodiment of the invention. In the figure, 4 and 4' indicate interface registers copoT and CnPORT between CPU Uo to CPUn. 5 is the boat LBPORT for the re-input signal;
6 is a priority control circuit.

7 to 13 are pipeline components denoted as TI to TI. Special KT7 is used to set a request resubmission command. 14 is a buffer B82, 15 is its address circuit, and 16 is a read data (RD
) register, 17 is! 18 is an input data register, and 19 is a write data (WD) register.

Further, 20 is a control memory BIMEM controlled by the output of pipeline T2, 21 is its address register BIAR, and 22 is n+l bit read data (
BI RD ) register, 23 is the convolution data (BI
The WD) register 24 determines which BS1 has the same data from the buffer comparison information read from the B I RD.
This is a BI logic circuit that determines the necessity of updating IMEM.

25 is a re-input (LB) logic circuit, which is controlled by the BI logic circuit and sets a pipeline re-input request to TI together with the convolution signal of BS2 when updating BIMEM; B, <If MEN is not updated, only the write signal for BS2 is sent to TI.
Set to .

8. In the embodiment circuit of FIG. 4, for the sake of simplicity, the processing for the storage device M8UK 31! The circuit portion is omitted from the illustration. Similarly, in the following operation description, it is assumed that the data requested to be accessed by the CPU exists in the BSI.

If there is no need to change BIMEMY, that is, when one CPU executes a store instruction, other CPUs
A case will be described in which the corresponding data is not included in BS1.

Assume that C0PORT4 receives an 8-byte partial write command (P8T) from CPU Uo.

After the priority of this command is determined by the priority control circuit 6, the P8T command is accepted by the address circuit 1 of the buffer B82.
When it is input to the control circuit of 5 etc., it is also K.

Pipeline (TI) K is introduced. Address circuit 15
From BS2 to RD register 16K.

The data is read out, and the merge circuit 17 inputs the input WD.
It is merged with the write data from register 18.

At this time, due to the control signal from T2 of the big line,
The buffer comparison information is also read from the HIM'EM 20.
The data correspondence between the BSI of each CPU and B8g is checked. Here, the area for armpit information other than CPUo is
When all are @0″″, CPU internal buffer B8
The command BIRQ to invalidate the data corresponding to
It is not output to U either.

In addition, in this case, BS1 and BS2 in the CP Uo
The data is updated based on the FAT command, but the buffer comparison relationship does not change at all, so there is no need to rewrite the buffer comparison information in BIMiiiM. therefore,
The BI logic circuit does not give an instruction to the LB logic circuit 25 to resubmit a request to the pipelines TI, T2, etc. At this time, the LB logic 31wA path 25 sets only the write signal to the single KB 82 to TI.

By the way, the updated data merged in busy merge time jl17 is written to BS, 2, so WD register 19
has been shifted to. Further, the write address to BS2 passes through TI and TI and is set in the address circuit 15 from LBPORT5. Here, the update data is folded into BS2 by the write signal from LBPORT.

In addition, B82 is 16 as explained in FIG.
Since it has a four-byte puncture configuration, access is prohibited for punctures caused by the above-mentioned 8-byte partial write command PST.

However, since other banks can operate independently, accesses to other banks can be put on the bigline.

Next, a case where it is necessary to change the BIMBMt-commitment will be described. As in the above case, COP 0 of CPUo
1L TK P 8 When the T command is accepted, the BS
The operation for 2 is done in exactly the same way. Also, B I
Reading of buffer comparison information from kiEM is also carried out at 9. Here, the BI logic circuit 24
When 11'' is detected in a region other than o, a command BIRQ for invalidating the de7 is issued to B81 of the CPU corresponding to the cough 11''.

Since the corresponding data in B81&C of other CPUY') B81&C is invalidated, the corresponding @1'' in BIMgMK's buffer comparison information is also invalidated, so two to seven update processes are required. According to the instruction from the logic circuit 24, the LB logic circuit 25&j.

Along with the write signal to B82, a pipeline re-input request for BIMEM update is set in T7.

Request for re-introduction of Pipe Twin is from BIMF! Contains update information of M, from T7, passes through LBPORT and the priority control circuit 6, and when B82 is subjected to convolution control, the TIK of the republic and pipe twin is re-introduced. The request re-submitted to BIG TWIN sets the necessary information from T2 to the BIAR register 21 and BIND register 23 of BIMEM, and executes the process of updating BIMBM to the latest information.
Execute in parallel with the write process.

(6) According to WIIIK, which is the basis for the effects of the invention, when writing 64 bytes of data using an 8-byte partial write command P8T, in parallel with the write operation of the buffer 7BS2, the control memo IJ
Since it is possible to update the buffer comparison information of B I M B M, taking into account the parallel processing of B82 punctures, it is possible to use pipe twins a total of 9 times, and the processing speed can be significantly improved. can.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a data processing system to which the present invention is applied, FIGS. The figure shows a diagram F14 of the buffer contrast information in BIMBM, and FIG. 4 is a circuit diagram of an embodiment of the present invention. -, 4.4' is a port for receiving instructions from the CPU, 5 is a re-input port from the end of the pipeline, and 7 to 1
3 is pipeline configuration 1! element, 14 is buffer B82,
15 is an address circuit, 16 is a read data register,
19 is a write data register, 20 is a control memory BI
MBM, 21 is an address register, 22 is a read data register, 23 is a write data register, 24 is a BI logic circuit regarding buffer comparison information, and 25 is an LB@filling circuit for controlling re-input of data. Patent Applicant: Fujitsu Limited Representative Patent Attorney Written by Yo Hase

Claims (1)

[Claims] a plurality of data processing devices having a first buffer used only by the data processing device itself, a second buffer that can be accessed by all of the plurality of data processing devices, and the second buffer and the first buffer;
In a data processing system 8, which has a control memory whose contents correspond to buffer 7, and which is equipped with a pipeline-controlled storage control device and a storage device, it is detected that the contents of the control memory need to be rewritten. and a request re-input circuit controlled by an error detection circuit, and when a store instruction is given, first inputs a request to perform convolution on the second buffer to the pipeline of the storage control device. and when the detection circuit detects the need to rewrite the contents of the control memory, it controls the request re-input circuit to re-input a request for rewriting the contents of the control memory to the pipeline. A storage access processing device.