JPS6079467A - Information processing system - Google Patents

Abstract

PURPOSE:To execute the succeeding scalar load command in the course of a vector store command operation processing by holding a vector in an address area register when it is being stored continuously to a prescribed distance address. CONSTITUTION:When a vector data store command is outputted to a register 7 from a commanding circuit 1, start address B, vector inter-element distance D and an element number E of store are set to registers 600-602. Data of the registers 600-602 are multiplied 603 and added 604, and set to vector store start and end adress registers 604, 605. When the succeeding scalar data load command 1' is outputted to a controlling circuit 6, it accesses to an area detecting circuit 12, tag storing circuit 8 and a buffer, and a scalar load SL controlling circuit 801 is started. In subtracters 700, 701, an SL address 116 is calculated with DXE+B and B, and unless outputs 703, 704 turn on an AND circuit 702, SL is executed. In such a way, a scalar arithmetic can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a plurality of interfaces to a scalar arithmetic processing unit having a scalar prior art buffer memory circuit and a main memory during vector data store processing, and accesses a plurality of vector element data simultaneously. In an information processing system having a parallel vector arithmetic processing device capable of processing, the contents of a buffer memory circuit possessed by the scalar arithmetic processing device are In order to guarantee this, the vector store address is sent to the buffer memory circuit and the tag storage circuit, and it is checked whether data corresponding to the vector store address is registered in the buffer memory. If it is registered, it is registered in the tag storage circuit. A method of providing an invalidation circuit for invalidating the corresponding address that is currently being used has been known in the past. In general, this invalidation operation is performed independently of the actual vector element store operation to the main memory, and there are also methods of providing multiple invalidation circuits to improve the processing efficiency of the invalidation operation. Are known.

However, by improving the processing efficiency of the invalidation operation in response to the vector store instruction, it is not possible to speed up instructions subsequent to the vector store instruction, especially scalar load instructions. In other words, during vector store processing (during vector store operation and invalidation processing operation), the data guarantee of the buffer memory circuit ends for subsequent scalar load instructions even if the requested scalar data exists in the buffer memory circuit. Since execution is suspended until the command is executed, the disadvantage is that it is not possible to speed up scalar instructions.

Purpose of the Invention The store operation of vector elements in a vector operation instruction can be roughly divided into ■ store operation to consecutive addresses, ■ store operation at each address of one foot distance, and ■ store operation to random addresses. Most of the operations are store operations. The object of the present invention is to calculate the start address and end address of the store address in advance during the store operation to consecutive addresses and the store operation to each address of one foot distance. An object of the present invention is to provide an information processing system that enables overtaking processing of vector store processing if the roto 9 address of the "ex-k" meeting does not fall within the vector store address area.

Structure of the Invention The system of the present invention comprises a main storage device and a buffer memory means having a data transmission/reception path between the main storage device and storing a copy of a part of the data in the main storage device; a tag storage means for registering block address information of the main storage device corresponding to stored data; a tag control means for controlling new registration of block address information in the tag storage means or invalidation of registered addresses; A command means for issuing load and store operation commands for data or scalar data, and in response to a vector store operation command from the command means, each store address for a plurality of vector element data generated in response to the command is set. tag registration invalidation instructing means for checking whether the registered address is registered in the tag storage means, and instructing the tag control means to invalidate the registered address if the registered address is registered; and the vector store. The store start address and store end address on the main memory at which the vector store is executed based on the operation command, the vector store start address generated with the command, the distance between vector element data, and the number of vector store elements. A vector store area storage means for storing data in an address area, and a subsequent scalar data load command from the command means before the operation of the tag registration invalidation command means is completed in response to the vector data store command? When receiving the command, area detection means checks whether the scalar data load address received along with the command is within the address area indicated by the vector store area storage means, and if it is within the area, outputs an in-area detection signal. and a scalar control means which is connected to the command means, buffer memory means and tag storage means and controls to relay the scalar load command processing when receiving an in-area detection signal from the area detection means. include.

Examples of the invention Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a command circuit l
, a plurality of vector processing units 2.3 and 4. Main memory 5. Nuka 2 - load control circuit 6, vector store address area register 7, tag circuit 8. Tag control circuit 9.
Buffer memory circuit 10, tag registration invalidation instruction circuit 11
．． Area detection circuit 12. and a scalar arithmetic circuit 13.

Referring to FIG. 2, the tag registration invalidation instruction circuit 11
is the start address register 201. vector element nJl
Distance register 202. Element number register 203, switching circuit 204. Adder input register 205° Adder 206. Vector address register 207° switching circuit 208. Subtractor 209. It consists of a subtraction result register 21O, a part of the vector store address control circuit 211° switching circuit 300, and a tag detection address register 301.

The tag storage circuit 8 includes a switching circuit 300. a part of the tag detection address register 301, a part of the tag memory 302,
""l# level signal 303.10" level signal 304,
It consists of a switching circuit 305 and a tag V bit memory 306.

The tag control circuit 9 is composed of a write address register 406 and AND registers 401 and 402.

The vector store address IJt area register 7 includes the start address register 600. It consists of a vector element distance register 6011, an element number register 602, a % multiplier 603, an adder 604, a vector end address register 605, and a vector store start address register 606. The area detection circuit 12 is composed of subtracters 700 and 701 and an AND game 702.

Next, the operation of this embodiment will be explained in detail.

Vector data store command is passed from command circuit l to path 101
When the data is transferred to the vector arithmetic processing device 2.3゜4, vector store address area register 7, and tag registration invalidation circuit 11, the vector arithmetic processing device 2,3
and 4 execute a vector store operation on the main storage device 5 via nodes 102, 103 and 104. In vector store address area register 7, path 1
The starting address of the vector store sent via 01 a3).

The distance between vector elements is 0 and the number of elements in the vector store (
Vector store start address is derived from the information of 0) and end address = start address 0 + distance between vector elements (g) x
Calculates the number of elements in the vector store and stores the result. Further, the tag registration invalidation circuit 11 determines the vector store address (C), CB1D) from the vector store information sent via the path 101.

CB+2D)s-...Create CB+EXD),
It is compared with the tag address information 108 in the tag storage circuit 8.

If the ratio matches, it indicates that the vector store address is registered in the tag storage circuit 8, so the vector store address is registered in the tag storage circuit 8.
In order to guarantee that each of the backup memory circuits 10 is not stolen when a vector store operation is performed on the main memory 5 when the door operation is executed, the blocks on the main memory of the data held in the backup memory circuit 10 are stored. A tag address to be invalidated and an invalidation instruction are transferred to the tag control circuit 9 via a path 109 so as to invalidate the block address of the tag storage circuit 8 in which the address is registered.

When the scalar load control circuit 6 receives a subsequent scalar data load command from the command circuit l via the path 106 while executing the tag registration invalidation process for the vector store command, the scalar load address information is transferred to the path 11.
6 through the area detection circuit 12vc% and the path 115'f
: Via the tag storage circuit 8 and the tag registration invalidation instruction circuit 1
1 and also via path 112 to buffer memory circuit 10
The data is then transferred together with the scalar load command signal.

When the scalar load command is sent, the area detection circuit 12 compares the scalar load address that is sent together with the output 105 of the vector store address area register 7.
It is compared whether the scalar load address is within the vector store address area, and if it is within the area, an inside area detection signal is sent to the scalar load control circuit 6 via path 107 and the scalar load operation is interrupted. .

If the in-area detection signal is not output, it is first checked whether the scalar load address is registered in the tag storage circuit 8 or not. The signal is sent to the scalar arithmetic circuit 13. Further, if the scalar load address is not registered in the tag storage circuit 8, the block data containing the scalar load address data is registered in the buffer memory circuit 10 from the main storage device 5 via the path 11. The Glock address including the scalar load address is also registered in the tag memory circuit 8 according to the instructions from the tag control circuit 9, and the scalar load data is read out again from the tufa memory circuit IO and the load data is sent to the Nuka 2-arithmetic circuit 13. .

Next, an embodiment of the tag storage circuit 8 and the tag registration invalidation instruction circuit 11 will be further described using FIG.

When a vector store command is sent from the command circuit 1 via the node 101, the start address of the vector store is sent together with the tag registration invalidation group 111C.

The distance between vector elements) and the number of elements in the vector store (g) are respectively stored in the start address register 201, the distance between vector elements register 202, and the number of elements register 2.
Set to 03.

The output of the start address register 201 is sent to the switching circuit 204.
The output of the vector element distance register 202 is sent to the adder 206 via n. Adder 206 adds the output of adder input register 205 and the output of vector element distance register 202, and the result is sent to switching circuit 204 and vector store address register 207. Vector address register 2
The output of 01 is sent to the tag search address register 301 in the tag storage circuit 8 every time the result of the adder 206 is set.
is set via the switching circuit 300.

The vector store address is transferred to the trc vector address register 207 as a vector store address the number of elements (set for the number of times, and transferred to the tag storage circuit 8). To create and transfer a vector store address, use the output of the number of elements register 203 to create and transfer a vector store address. This is repeated until the circuit 211 detects zero. The switching circuits 204, 208 and 300 are controlled by a vector store address control circuit 211. Details a
The explanation of fx tIII operation is omitted because it has no bearing on the present invention.

When a vector store address is set in the tag search address register 301, the lower block address of the address is transferred to the tag memory 302 via a path 307.
The tag is sent to the tag V set memory 306, the corresponding block address and the V bit are read out, and the comparison circuit 212
, 213 and AND gates 214 and 215. The technical memory of this embodiment has two components (
level) fl-thinking.

In the comparison circuits 212 and 213, the tag memory 30
The output of 2 is compared with the upper block address information of the tag search address register 301, and the comparison result is an AND game)
At 214 and 215, the output of the tag v bit memory 306 is ANDed for each level. Comparison circuit 212 or 213 indicates that the comparison match is jL, and the tag v bit memory 3 indicates the validity of the corresponding block address.
If the output of 06 is '1'', level @0'' match flag register 218 or level l match flag register 219
The logical sum of the coincidence signals of both levels n1 and n1 is taken by the zero gate 220, and a bit signal is set in the bit display flag register 217.

When the hit display flag register 217 is set, the address information in the lower block of the tag search address register 301 is set in the invalidation address register 216 and transferred to the tag control circuit 9 via the path 109. In the tag control circuit 9, the output of the hit display flag register 217 is logically ANDed with the timing signal by an AND gate 401, and A is stored in the tag V bit memory 306 in the tag storage circuit 8.
This is shown by the output of the ND game (ND game) 402. An instruction signal is sent along path 114 with the output of the invalidate write address register 400 to set the V bit of the tag V bit memory 306 to 10''. The output of the @O'' level signal 304 is selected by the switching circuit 305 as the write input for the write operation.The above is an explanation of the invalidation processing method for the vector store address of the tag storage circuit 8.

Next, the vector store address area register 7 and area detection circuit 12V, which are features of the present invention, will be explained using the embodiment block diagram of FIG.

Vector data store command is passed from command circuit l to path 101
The start address a of the vector store is sent together with the vector store address area register 7 through all
3), the distance between vector elements (b) and the number of elements in the vector store are set in the start address register 600. It is set in the vector element distance register 601 and the element number register 602.

The output of start address register 600 is sent to adder 604 and vector store start address register 606.

The outputs of the inter-element distance register 601 and the number of elements register 602 are input to the multiplier 603, and the vector inter-element distance (goods) is inputted to the multiplier 603.
×Number of elements of vector store (output of Q is input to adder 604, start address skewer from adder 604) + distance between vector elements Set to 1. These two registers 605 and 60
The contents of 6 are valid until the vector store address control circuit 211 detects that the number of remaining vector elements is zero. In other words, the contents of the vector store start address register 606 and the vector store end address register 605 are valid only while tag registration invalidation processing is being executed in response to a vector data store command, and are not valid during other periods, for example. All of them are set to a value of 10" and have a passionate content.

When the values in the registers 605 and 606 are set and the subsequent Nuka2 data load command is issued from the command circuit 1 to the scalar load control circuit 6 while the tag registration invalidation process is being executed, the command is transferred together with the scalar load control circuit 6. . Along with the scalar data load address information, it generates an access control signal to the area detection circuit 12, tag storage circuit 8, buffer memory circuit IO, etc. The scalar load control circuit 801 is activated, and the scalar load address information is transmitted to the area detection circuit 12,
The data is sent to a tag storage circuit 8 and a buffer memory circuit 10.

In the area detection circuit 12, a subtracter 700 subtracts the scalar load address information 116 from the output of the vector store end address 605, and if the result sign is a positive value, subtraction is possible (
Carry out) signal 703 is issued. On the other hand, the subtracter 701 conversely subtracts the output of the vector store start address register 606 from the scalar load address information 116, and similarly, if the result is a positive value, a subtractable (carry out) signal 704 is output.

That is, the signal 703 and the signal 704 are connected to the AND gate 70
If 2 is AND% n, it means that the scalar load address is between the vector store start address and the vector store end address. In this case, there is a possibility that the scalar data load address and the vector data address match69, so if the scalar data load is executed to Kl where the tag registration invalidation process ends, the contents of the main memory 5 will be changed in the vector store. However, the result is that the contents of the buffer memory circuit IO before the change are loaded. Therefore, when the AND condition is violated in the AND gate 702, a scalar load inhibit signal 107 is sent to the scalar load control circuit 6 to interrupt the scalar load process.

Effects of the Invention The present invention has the advantage that all subsequent scalar load commands can be executed during vector store command operation processing.

[Brief explanation of the drawing]

Fig. 1 shows an embodiment of the present invention, Fig. 2 shows a 4111
FIG. 3 is a diagram showing the detailed configuration of the tag registration invalidation instruction circuit and tag storage circuit of FIG. 1, and FIG. 3 is a diagram showing the entire detailed configuration of the vector store address area register and area detection circuit of FIG. In FIGS. 1 to 3, l...command circuit,
2, 3. 4...Vector arithmetic processing device, 5
. . . Main memory, 6 . . . Scalar load control circuit, 7 . . . Vector store address area register, 8 . . . Tag storage circuit, 9 .・
. . . Tag control circuit, 10 . . . (rough memory circuit, 11 . . . Tag registration invalidation instruction circuit, 12)
... Area detection circuit, 13 ... Scalar arithmetic circuit, 14 ... Scalar arithmetic processing device, 20
1...Start address register, 202...
...Vector distance register, 203...
Prime number register, 204...Switching circuit, 205
...Adder input register, 206...
Adder, 207...Vector store address register, 208...Switching circuit, 209...
...Subtractor, 21O...Subtraction result register,
211...Vector store address control circuit,
212゜213... Comparison circuit, 214.215
--- AND game), 216 --- Invalidation address register. 217...Hit display flag register, 218
・・・・・・Level O-T F2 register, 219...
...Level l match flag register, 220...
...O1t gate, 300...Switching circuit, 30
1...Tag search address register, 302...
...Tag memo 1c 303...''l level signal, 304...'0'' level signal, 305.
...Switching circuit, 306...Tag v pit memo 1c 400...Focusing write address register, 401...ANI) gate, 402...
...AND gate, 600...Start address register, 601...Vector element distance register, 602...Number of elements register, 603...
... Multiplier, 604 ... Adder. 605...Vector store end address register, 606...Vector store start address register, 700...Subtractor, 701...
・Subtractor, 702...ANI) gate, 703
,704...Subtractable signal.

Claims (1)

[Claims] A main storage device. At least one vector processing device that has at least one data transmission/reception path with the main storage device and can simultaneously access a plurality of vector element data in the main storage device, and the main storage device. A scalar arithmetic processing unit with data transmission and reception paths. In an information processing system, the information processing system includes command means for issuing load and store operation commands for vector data or scroller data to the vector arithmetic processing unit or the scalar arithmetic processing unit according to program instructions, a buffer memory means having a transmission/reception path and storing part of the data in the main storage device; a tag memory for registering block address information of the main storage device corresponding to data stored in the buffer memory means; means, tag control means for controlling new registration of block address information in the tag storage means or invalidation processing of registered addresses; It is checked whether or not each store address for a plurality of vector element data is registered in the tag storage means, and if it is registered, the tag control means is instructed to invalidate the registered address. A tag registration invalidation instructing means for instructing, and a vector store operation command based on the vector store start address, the distance between vector element data, and the number of vector store elements generated in accordance with the vector store operation command. vector store area storage means for storing a store start address and store end address on main memory to be executed as an area; When a subsequent scalar data load command is received from the scalar data load command, it is checked whether the scalar data load address received along with the command is within the address area indicated by the vector store area storage means, and if the address is within the area. A region detecting means for outputting an in-area detection signal when the pick is connected to the command means, the buffer memory means, and the tag storage means, respectively, and upon receiving an in-area detection signal from the area detecting means, outputs a scalar load command. An information processing system comprising: a mechanism 2-load control means for controlling to interrupt processing.