JPS61289464A - Scalar arithmetic processor - Google Patents

Abstract

PURPOSE:To improve the processing capacity of the titled device by controlling the processing so as to prevent data newly block loaded in each block from a main memory device during the invalidating processing of tag registeration from unnecessary operation due to the succeeding scalar loading instruction or tag registration invalidating request. CONSTITUTION:When the succeeding scalar data loading request or tag registration unvalidating request is inputted, the contents of a buffer updating address register 505 is compared with a block address by a comparator 507, and when the coincidence is detected by the comparator 507, a signal on a signal line 119 is turned to '0' so as to suppress an intra-area detecting signal against said scalar data loading request even if the intra-area detecting signal is sent from a signal line 703 to suppress the generation of a buffer mishit. Against the tag registration invalidating processing request, a suppress signal is sent to a buffer timing control part 503 through a signal line so as to suppress the tag registration invalidating processing of an address concerned.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a scalar arithmetic processing device used together with a plurality of vector arithmetic processing devices, and in particular to a buffer invalidation control method for vector data store processing and a vector delta store processing. Regarding the scalar data load processing method.

(Prior Art) A scalar arithmetic processing device equipped with a buffer memory circuit and a parallel vector arithmetic processing device that has a plurality of interfaces to a main memory and can access a plurality of vector element data simultaneously. In an information processing system having a scalar arithmetic processing unit, a vector address is stored in order to guarantee the contents of a buffer memory circuit provided with a scalar arithmetic processing unit in response to a store operation of a vector element to the main memory fK performed by a vector arithmetic processing unit. Sends data to the buffer memory circuit and tag storage circuit, checks whether an address corresponding to the vector store address is registered in the tag storage circuit, and if registered, invalidates the corresponding address. Systems with circuits were known.

Furthermore, this invalidation processing operation is performed independently of the actual vector element data storage operation to the main memory, and
A system including a plurality of invalidation processing circuits in order to improve the efficiency of the invalidation processing operation has also been known.

(Problem to be Solved by the Invention) However, simply improving the processing efficiency of the invalidation processing operation corresponding to the vector store instruction cannot speed up the execution of instructions subsequent to the vector store instruction, especially scalar load instructions. Can not. That is, during vector store processing, including vector store operation and invalidation processing operation, subsequent scalar load instructions are not executed even if the buffer memory circuit has the requested scalar data.
Since the execution is suspended until the data guarantee of the buffer memory circuit ends, there is a drawback that the execution of the scalar load instruction cannot be accelerated.

An object of the present invention is to continue a subsequent scalar load instruction without interrupting processing during tag registration invalidation processing for a vector store command, and to prevent data that has been newly loaded from the main memory into a block during tag registration invalidation processing. The above disadvantages are eliminated by controlling subsequent scalar load instructions and tag registration invalidation requests so that they do not perform unnecessary operations, and the scalar load instructions are configured to be executed at high speed. An object of the present invention is to provide a scalar arithmetic processing device that performs the following steps.

(Means for Solving the Problems) A scalar arithmetic processing device according to the present invention includes a main storage device connected by a data transmission/reception bus, and a main storage device connected to the main storage device by at least one data transmission/reception bus,
at least one vector processing unit configured to be able to access vector element data in the main memory; and a command configured to be able to send load/store operation commands for vector data or scalar data in accordance with program instructions. It constitutes an information processing system together with the circuit, and includes a backup memory circuit,
It is configured to include a tag storage circuit, a tag control circuit, a tag registration invalidation instruction circuit, a vector store address area register, an area detection circuit, and a buffer control circuit provided with address holding means.

The backup memory circuit has a data transmission/reception bus with the main memory and is used to store a copy of part of the data in the main memory.

The tli circuit is for registering block address information of the main memory device in correspondence with data stored in the buffer memory circuit.

The tag control circuit is for controlling new registration of block address information in the tag storage circuit or invalidation processing of registered addresses.

The tag registration invalidation instruction circuit responds to a vector data store operation command from the command circuit and determines whether each store address is registered in the tag storage circuit for a plurality of vector element data generated in response to the command. This is to check if the registered address is registered, and if it is registered, to instruct the tag control circuit to invalidate the registered address.

The vector store address area register is for outputting a store start address and a store end address on the main memory as areas in response to a vector store operation command.

The area detection circuit is for outputting a store start address and a store end address on the main memory as an area in response to a vector store command.

When the area detection circuit receives a subsequent scalar data load command from the command circuit before the tag registration invalidation command circuit completes its operation in response to the vector store command, the area detection circuit detects the scalar data load address received with the command. This is to check whether the address area is within the address area indicated by the vector store address area register, and to output an in-area detection signal if it is within the area.

When the in-area detection signal is detected, the address holding means assumes that the scalar load block address corresponding to the scalar load command is not registered in the tag storage circuit based on the detection signal, and stores the scalar load block address in the main memory. The block address corresponding to the block data transfer is held together with the validity indicating pit until the operation of the tag registration invalidation instruction circuit corresponding to the vector store command is completed.

In addition to the address holding means, the buffer control circuit responds to a subsequent scalar data load instruction, compares the block address part of the scalar data load address received with the command and the contents of the address holding means, and detects a match. and block data transfer to the main memory in response to the corresponding scalar data load command, and the invalidation address sent in response to the invalidation instruction from the tag registration invalidation instruction circuit matches the block address of the address holding means. This is to control such that when a corresponding invalidation instruction is detected, the corresponding invalidation instruction is suppressed.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

First, the general operation of a basic configuration example including a scalar arithmetic processing device according to the present invention will be explained with reference to FIG. In FIG. 1, 1 is a command circuit, 2 to 4 are vector processing units, 5 is a main memory, 6 is a buffer control circuit, 1 is a vector store address area register, 8 is a tag storage circuit, and 9 is a tag control circuit. circuit, 10 is a buffer memory circuit, 11 is a tag registration invalidation instruction circuit, 12
13 is a scalar arithmetic circuit, and 14 is a scalar arithmetic processing device.

In FIG. 1, a vector data store command is sent from a command circuit 1 via a signal line 101 to a vector arithmetic processing device 2 to
4 and is transferred to the tag registration invalidation circuit 11. Vector arithmetic processing devices 2-4 execute vector store operations on main storage device 5 via signal lines 102-104. Although three vector arithmetic processing devices are shown in FIG. 1, they are not directly related to the present invention. The vector store address area register circuit 7 receives the vector store start address (B), the distance between vector elements (D), and the number of vector store elements ( E) to vector store start address (B) and end address (=(B)±(D
)X(E)) and hold these addresses as area addresses on the main memory 5.

The tag registration invalidation circuit 11 generates vector store addresses (B) and (B+D) based on the vector store information sent via the signal line 101.

(B+2D), ---(B+EXD) are created and sent to the buffer control circuit 6 via the signal line 117 along with a buffer invalidation request (not shown). In response to the invalidation request, read addresses of the tag storage circuit 8 and backup memory 10 are sent from the buffer control circuit 6 via the signal line 109, and the tag address information read from the tag storage circuit 8 onto the signal line 108. (block address information) and the signal line 10 from the buffer control circuit 6
The block address portion of the vector store address sent via the tag control circuit 9 is compared. As a result of the comparison, a match indicates that the vector store address is registered in the tag storage circuit 8. Therefore, after the vector store operation is executed, the buffer memory in which the vector store operation is not performed on the contents of the main memory device 6 is It is necessary to guarantee the contents of the circuit 10. The block address of the data held in the backup memory circuit 10 with respect to the main storage device 5 is registered in the block address of the tag storage circuit 8. instructions are transferred via signal line 114.

During the period in which tag registration invalidation processing for such a vector store command is being executed, a subsequent scalar data load command is sent from the command circuit 1 to the buffer control circuit 6 via the signal line 106, and the packer control circuit 6 When received, the scalar load address information is sent to the area detection circuit 12 via the signal line 116, and sent to the tag storage circuit 8, the tag control circuit 9, and the backup memory circuit 10 via the signal line 119, along with a scalar load command signal. be done. Upon receiving the scalar load command, the area detection circuit 12
Then, the scalar load address sent together with the scalar load command is compared with the output of the vector store address area register 7 on the signal line 105 to determine whether the scalar load address is within the vector store address area. When the scalar load address falls within the area, an in-area detection signal is sent to the buffer control circuit 6 and the tag control circuit 9 via the signal line 107.

The buffer control circuit 6 treats the corresponding scalar load command as a buffer miss and directly sends a block load request to the main storage device 5 via the signal line 118.

The loaded data from the main storage device 5 in response to this block load request is registered in the cache memory circuit 10 via the signal line 111, and the requested data is returned to the scalar arithmetic circuit.

If the area detection signal is not sent, it is first checked whether the scalar load address is registered in the tag storage circuit 8, and if it is registered, the scalar data read from the backup memory circuit 10 is sent via the signal line 113. and sent to the scalar arithmetic circuit 13.

If the scalar load address is not registered in the tag storage circuit 8, block data including the scalar load address data is registered in the buffer memory circuit 10 from the main storage device 5 via the signal line 111, and the scalar load address is not registered in the tag storage circuit 8. A block address including the address is registered according to an instruction from the tag control circuit 9, and the requested data is returned to the scalar calculation circuit 15.

Next, the buffer control circuit 6, tag storage circuit 8, tag control circuit 9, and tag registration invalidation instruction circuit 11 according to the present invention will be explained in more detail with reference to FIG.

In the buffer control circuit 6 in FIG. 2, 500 is a scalar load control circuit, 501 is a switching circuit, 502 is a tag search address register, 605 is a cache timing control section, 504 is a switching circuit, 605 is an update address register, and 506 is a A valid bit flag register, 501 is a comparison circuit, 508 is a NAND gate, and 509 is an AND gate.

In the tag storage circuit 8, 301 is a tag memory, 303
is a switching circuit, 306 is a tag V bit memory, in the tie control circuit 9, 401 and 402 are comparison circuits, 405 and 404 are AND/NAND gates, 405 is a NAND gate, 406 is an invalidation address register, and 407 is a A pit display flag register, 408 is a level 0 match flag register, 409H is a level 1 match flag register, 410 and 411 are AND gates, and 412 is a NAND gate. In the tag registration invalidation instruction circuit 11, 201 is a start address register;
2 is a vector element distance register, 20S is an element number register, 204 is a switching circuit, 205 is an adder input register, 206 is an adder, 207 is a vector store address register, 208 is a switching circuit, 209 is a subtracter, 21
0 is a subtraction result register, and 211 is a vector store address control circuit.

In FIG. 2, when a vector store command is sent from the command circuit 1 to the tag invalidation circuit 11 via the signal line 101, the vector store start address (B) and the distance between vector elements are sent together with the vector store command. (D)
, and the number of elements (E) of the vector store are set in the start address register 201, vector interelement distance register 202, and number of elements register 203, respectively.

The output of the start address register 201 is sent to the switching circuit 204.
The output of the vector element distance register 202 is sent to the adder 206 via the adder input register 205 . In the adder 206, the adder input register 206
and the output of the vector inter-element register 202, and the result is sent to the switching circuit 204 and the vector store address register 207.

The output of the vector address register 207 is sent to the adder 206
Each time the result is set, a buffer invalidation request is sent to the buffer control circuit 6 via the signal line 117, and the tag search address register 502 is sent to the switching circuit 5.
Set via 01. In addition, the vector address register 207 contains the vector store address as element (E).
The number of elements (E) is created as many times as the number of times, and the number of elements (E) is
are transferred as vector store addresses.

In this embodiment, the switching control of the switching circuit 601 is not explained in detail, but the timing at which the scan load/store request is sent from the signal line 506' and the buffer invalidation from the vector address register 207 via the signal line 117 are explained in detail. If the timing coincides with the sending of the request, the scan load/stop request is processed with priority, and the processing of the tag invalidation circuit 11 must be stopped during that time. For these controls, a commonly considered request competition control method may be applied, and detailed explanations will be omitted since they are not directly related to the present invention. In the tag invalidation circuit 11, the vector store address is created and transferred using the element number register 203 until zero is detected in the vector store address control circuit 211.
It is executed based on the output of

When a vector store address is set in the tag search address register 502, the lower block internal address part of the above address is sent to the tag memory 301 and the tag V bit memory 305 via the signal line 109, and the corresponding block address and V The bit is read and the comparison circuit 40
1.402, as well as AND gate 405.404. In this embodiment, the buffer memory is assumed to have two compartments (two levels).

Comparison circuits 401 and 402 compare the output of the tag memory 301 and the upper block address information of the tag search address register 502, and the comparison results are ANDed (AND game) 405,
At 404, the output of the tag V bit memory 305, the level, and K are each subjected to an AND condition. Comparison result 401,
Alternatively, as a result of the comparison in the comparator circuit 402, a match is found, and the output of the tag V bit memory 506 indicating the validity of the block address is %11, and as will be explained later, from the NAND gate 412. signal line 41
If the hit valid signal outputted on 5 is %11, the level low match flag register 40B and the matach level 1 match flag register 409 are set, and the logical sum of the match signals at both levels is calculated by the NAND game 406, and the hit valid signal is %11. A signal is set in the hit display flag register 401.

When the hit display flag register 407 is set, the tag search address register! At the lower level of I02, in-lock address information is set in the invalidation address register 406, and the output is transferred to the tag storage circuit 8. The output of the hit display flag register 407 is applied to an AND gate 410, where an AND condition is determined between the output and the timing signal sent from the buffer timing control section 603 of the buffer control circuit 6 via the signal line 510. Tag memory circuit 8
The output of the register 406 is sent as an instruction signal via the signal line 114 to set the level V bit indicated by the output of the AND gate 411 to 10I for the tag V bit memory s05 in the tag V bit memory s05. It is sent with Here, the switching circuit 303 selects the %Ol level signal, and changes the v bit of the tag V bit memory 305 to %Ol.
Provided as a write input to set I.

The above is the explanation of the invalidation processing method for the vector store address of the tag storage circuit 8.

Before explaining the details of the buffer control circuit 6, which is a feature of the present invention, the vector store address area register 7 and the area detection circuit 12 will be explained with reference to FIG. In the vector store address area register 7 of FIG. 8, 600 is a start address register, 601
is a vector element register, 602 is an element number register,
603 is a multiplier, 604 is an adder, 605 is a vector store end address register, and 606 is a vector store start address register. In the area detection circuit 12, 700 and 701 are subtracters, and 702 is an AND gate.

In FIG. 3, a vector data store command from a command circuit 1 is transmitted to a signal line 11 via a tag registration invalidation circuit 11.
6 to the vector store address area register 7, the vector store start address (B), the distance between vector elements (D), and the number of vector store elements (
E) are the start address register 600, vector element distance register 601, and element number register 60, respectively.
Set to 2. The output of starting address register 600 is sent to adder 604 and vector store starting address register 606. The outputs of the inter-element distance register 601 and the number of elements register 602 are input to the multiplier 603, and the output of DXE is input to the adder 604.
4 to B+DXE are set in the vector store end address register 605. Until the vector store address control circuit 211 detects that the number of vector remaining elements is zero, the vector store end address register 6
05 and vector store start address register 606
The content of is valid. In other words, the contents of the vector store start address register 606 and the contents of the vector end address register 605 are valid only during the execution period of tag registration invalidation processing for a vector data store command, and are not cleared during other periods. has invalid content.

Certain values are set in the vector store end address register 605 and the vector store start address register 606, and tag registration invalidation processing is performed.

When a subsequent scalar data load command is sent from the command circuit 1 to the buffer control circuit 6 during execution of the scalar data load command, the scalar load control circuit 500 is activated and the scalar data load address information transferred with the subsequent scalar data load command is used. Access control signals to area detection circuit 12 and tag check address register 502 are generated. Therefore,
A scalar data load address is sent to area detection circuit 12 and tag search address register 502. In the area detection circuit 12, a subtracter 700 subtracts the scalar data load address on the signal line 116 from the output of the vector store end address register 605, and if the sign of the result is a positive value, a subtraction possible (carry aud) signal is output. It is sent out on line 703. On the other hand, the subtracter 701 subtracts the output of the vector store start address register 606 from the scalar data load address on the signal line 116,
Similarly, if the result is a positive value, the subtractable signal is on the signal line 70.
Sent on 4th. That is, the signal line 10s and the signal line 70
If the above condition is obtained by the KAND gate 702 to calculate the logical product between the vector store start address and the vector data store end address, the scalar data load address is between the vector store start address and the vector data store end address.

In the above case, there is a possibility that the scalar load address and the vector data store address match, and if the scalar data is loaded from the backup memory circuit 10 before the tag registration invalidation process is completed, the vector store will cause the vector data store address to match. This results in loading the contents of the backup memory circuit 10 before the change even though the contents of the backup memory circuit 10 are about to be changed. Therefore, if the logical product condition is obtained at the AND gate 102, an intra-area detection signal is sent to the buffer control circuit 6 and the tag control circuit 9 via the signal line 105.

Returning once again to the explanation of the operations of the buffer control circuit 6 and tag control circuit 9 in FIG. 2. When the in-area detection signal is input to the NAND gate 412 via the signal line 703, the input conditions of the NAND gates 403 and 404 are inhibited if the signal power βII from the buffer control circuit 6 is on the signal line 119. The scalar data load command at this time results in a buffer miss, and the scalar data load address is sent from the address register 502 through the switching circuit 604, and sent to the main memory as a block load address via the signal line 118. There is. As a result, the contents of the backup memory circuit 10 and the tag storage circuit 8 are updated, and the requested scalar data is sent to the scalar arithmetic circuit 1iSK. At this time, the block load address is set in the buffer 7 update address register 505 along with the valid bit 506 until the tag registration invalidation process is completed.

In this state, when a subsequent scalar data load request or tag registration invalidation processing request arrives, the contents of the buffer update address register 506 and the block address are compared by the comparison circuit 507, and a match is detected by the comparison circuit 507. Even if the within-area detection signal is sent from the signal line 703, the signal on the signal line 119 is changed to %OI so as to suppress the within-area detection signal in response to the former scalar data load request.
to avoid buffer misses.

In response to the latter request for tag registration invalidation processing, the buffer timing control unit 505 sends a message via the signal line 119 to suppress the tag registration invalidation processing for the corresponding address.
A suppress signal is sent.

(Effects of the Invention) As explained above, the present invention allows the subsequent scalar load command to continue without interrupting processing during tag registration invalidation processing for a vector store command, and to To control the data newly block loaded from the device so that subsequent scalar load commands and tag registration invalidation requests do not perform unnecessary operations.
This has the effect of improving processing performance.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a system including a scalar arithmetic processing device according to the present invention. FIG. 2 is a block diagram showing details of a buffer control circuit, a tag storage circuit, a tag control circuit, and a tag registration invalidation instruction circuit in the scalar arithmetic processing device shown in FIG. FIG. 8 is a block diagram showing details of a vector store address area register and an area detection circuit in the scalar arithmetic processing device shown in FIG. 1. 1...Command circuits 2-4...Vector arithmetic processing device 5...Main storage device 6...Buffer control circuit 7-11 Vector store address area register, 8-
・Tag storage circuit 9 ・・Tag control circuit 10 ・Bazza memory circuit 1111 ・No. tag registration invalidation instruction circuit 12 ・・Area detection circuit 13 ・・Scalar operation circuit 14 ・φ・Scalar operation processing device 201・-1 start address register 2G2 ・Fist vector inter-element distance register 2011 ・・Element number register 204.208. i$03.601.504-・-・・
Switching circuit 20! i... Adder input register 206.604... Adder 207... Vector address register 209.700
．． 701.@Φ subtractor 210...subtraction result register 211...Vector store address control circuit 501.
・-Tag memory 305--Tag V bit memory 401.402.507・Fist・Comparison circuit 40B, 404
...AND/NAND gates 406, 412, 508...NAND gate 406...invalidation address registers 407 to 409, 606...7 lag register 410.
411.609.702 - AND gate 500 - Scalar load control circuit 602 - Fist tag search address register 505 - Cache timing control unit 50.6 - Update address register 600 - Start address register 601a... Vector inter-element register 602... Element number register 60 &... Multiplier 605... Vector store start address register of 1 vector store end address register 606-...

Claims (1)

[Claims] A main storage device connected by a data transmission/reception bus; and a main storage device connected to the main storage device by at least one data transmission/reception bus, and configured to be able to access vector element data of the main storage device. scalar arithmetic processing for configuring an information processing system together with at least one vector arithmetic processing device and a command circuit configured to be able to send load/store operation commands for vector data or scalar data in accordance with program instructions; The device has a data transmission/reception bus with the main storage device, a buffer memory circuit for storing a copy of a part of the data in the main storage device, and a buffer memory circuit corresponding to data stored in the buffer memory circuit. a tag storage circuit for registering block address information of the main storage device; a tag control circuit for controlling new registration of the block address information in the tag storage circuit or invalidation processing of registered addresses; and the command circuit. In response to a vector data store operation command from the controller, it is checked whether or not each store address is registered in the tag storage circuit for a plurality of vector element data generated in accordance with the command, and whether or not each store address is registered in the tag storage circuit is checked. a tag registration invalidation instructing circuit for instructing the tag control circuit to invalidate the registered address if the vector store operation command is received; and a store start address and store end address on the main memory in response to the vector store operation command. If a vector store address area register that outputs as an area and a subsequent scalar data load command are received from the command circuit before the tag registration invalidation command circuit completes its operation in response to the vector store command, checking whether a scalar data load address received with the command is within the address area indicated by the vector store address area register;
an area detection circuit for outputting an in-area detection signal if the in-area detection signal is within the area, and a scalar load block address corresponding to the scalar load command in the tag storage circuit based on the detection signal when the in-area detection signal is detected. It is assumed that the block data corresponding to the scalar load block address is not registered, and the block data corresponding to the scalar load block address is transferred to the main storage device. The block address part of the scalar data load address received in response to a subsequent scalar data load instruction is provided with an address holding means for holding a block address corresponding to a block data transfer together with a validity indicating bit. The contents of the address holding means are compared, and if a match is detected, block data transfer to the main storage device in response to the corresponding scalar data load command is inhibited, and in response to an invalidation instruction from the tag registration invalidation instruction circuit. It is characterized by comprising a buffer control circuit for controlling the invalidation instruction to be suppressed when a match between the invalidation address sent along with the block address of the address holding means is detected and the corresponding invalidation instruction is suppressed. A scalar arithmetic processing unit.