JPS5797168A - Buffer nullification control system - Google Patents
Buffer nullification control systemInfo
- Publication number
- JPS5797168A JPS5797168A JP55172264A JP17226480A JPS5797168A JP S5797168 A JPS5797168 A JP S5797168A JP 55172264 A JP55172264 A JP 55172264A JP 17226480 A JP17226480 A JP 17226480A JP S5797168 A JPS5797168 A JP S5797168A
- Authority
- JP
- Japan
- Prior art keywords
- address
- comparing
- buffer
- read
- nullification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To efficiently execute a buffer nullification control, by providing (n) pieces of buffer nullification address detecting means and (n-1) pieces of comparing circuits for comparing a store address, and forcibly outputting the dissidence by the (i+1)-th buffer nullification address detection means. CONSTITUTION:A store address A from a vector unit is set to a tag access register 11, a tag part 15 is read-accessed by a lower bit, a read-out data is set to a read-out data register 23, and an upper bit of the store address A is set to a comparing address register 19. A comparing circuit 27 compares the contents of the comparing address register 19 with those of the tag read-out data register 23, and when both have coincided, the coincidence is outputted. A comparing circuit 31 compares a line address part of the store address A with a line address part of a store address B, and when the comparing circuit 31 outputs the coincidence, an output of a comparing circuit 28 is forced to dissidence.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55172264A JPS6059621B2 (en) | 1980-12-06 | 1980-12-06 | Buffer invalidation control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55172264A JPS6059621B2 (en) | 1980-12-06 | 1980-12-06 | Buffer invalidation control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5797168A true JPS5797168A (en) | 1982-06-16 |
JPS6059621B2 JPS6059621B2 (en) | 1985-12-26 |
Family
ID=15938667
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55172264A Expired JPS6059621B2 (en) | 1980-12-06 | 1980-12-06 | Buffer invalidation control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6059621B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61141054A (en) * | 1984-12-14 | 1986-06-28 | Nec Corp | Information processor |
JPS61264455A (en) * | 1985-05-18 | 1986-11-22 | Fujitsu Ltd | Coinciding and controlling system for main storage |
JPH02294866A (en) * | 1989-05-10 | 1990-12-05 | Hitachi Ltd | Storage control system |
JPH03231365A (en) * | 1990-02-07 | 1991-10-15 | Koufu Nippon Denki Kk | Information processor |
-
1980
- 1980-12-06 JP JP55172264A patent/JPS6059621B2/en not_active Expired
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61141054A (en) * | 1984-12-14 | 1986-06-28 | Nec Corp | Information processor |
JPH0211931B2 (en) * | 1984-12-14 | 1990-03-16 | Nippon Electric Co | |
JPS61264455A (en) * | 1985-05-18 | 1986-11-22 | Fujitsu Ltd | Coinciding and controlling system for main storage |
JPH0444975B2 (en) * | 1985-05-18 | 1992-07-23 | Fujitsu Ltd | |
JPH02294866A (en) * | 1989-05-10 | 1990-12-05 | Hitachi Ltd | Storage control system |
JPH03231365A (en) * | 1990-02-07 | 1991-10-15 | Koufu Nippon Denki Kk | Information processor |
Also Published As
Publication number | Publication date |
---|---|
JPS6059621B2 (en) | 1985-12-26 |
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