JPS5841478A - Cache storage device - Google Patents

Abstract

PURPOSE:To realize a removable cache storage device inexpensively, by writing the data to the cache storage device with the memory data line and transferring the readout data to an operation section via a memory data line. CONSTITUTION:At the readout of a main storage device, a main storage device address transmitted via an address line 1 is set to a memory address register 45 of a main storage control section 40. This address is set to an address register 23 of a cache storage device 20 via a memory address line 3 to access an address array 22 and a cache memory 21. When the data exist in the cache memory 21, the readout data is given to an operation section of a processor via a data line 6. In writing to the cache storage device 20, the data transmitted on the memory data line 4 is set to a write data register 24 and written in the cache memory 21.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to cache storage as an additional feature to improve the performance of relatively small processing devices.

Cache storage devices have traditionally been used as an essential means to improve the performance of large processing devices. Therefore, it was designed with emphasis on performance, and no emphasis was placed on quantity or price.

However, with recent advances in LSI technology, there is a movement to adopt cache storage devices as additional functions even in small processing devices where price is an important consideration. in this case,
It is desirable that the cache storage device be configured as a mounted module that can be attached to and removed from the processing device, and that the increase in the amount of basic parts be minimized. Furthermore, an appropriate balance between the presence or absence of additional functions and the price is also required.

FIG. 1 is a block diagram showing an example of a conventional cache storage device.

Regarding the cache storage method, see [Cache Memory System α), (2)'' Information Processing vol. 1.13.
A7 +P p 467-473 and A8.
p p540-547α97
J information processing vol. 1.21. A4+ PP332-34
-0 (1980) etc., but the first
The basic operation will be explained based on the diagram.

The cache storage device [20] checks the validity of data stored in the cache memory 21, and an address array 22. It consists of an address register 23 for holding the above-mentioned storage device address, a write data register 24 for holding data for updating the cache, and a data register 25 for holding all the data consecutively received from the cache memory 21.

The main 100 million control unit 40 includes a memory write data register 41 that holds main memory update data. Code creation section 42 that creates all error correction codes. A checking unit 43 that inspects the data read from the host Vi device and creates corrections and parity. A memory data register 44 to hold corrected data and a memory address register 46 to hold main memory addresses are included.

When performing a read operation to the cache memory, all addresses sent through the address line 1 are set in the address register 23, and the address array 22t' is accessed to check whether the data held in the cache memory 21 is valid or not. Find out. If this is valid, the data read from the cache memory 21 is set in the all data register 25 and sent to the arithmetic unit via the data line 6.

If the address is not registered in the cache memory 21, the address written by the address M1 is set in the memory address register 5 of the main memory control unit 4.0, and the readout from the main memory is performed. conduct. After a certain period of time, the read data is sent to the checking section 43 via the memory data line 5, where necessary corrections are made, and then set in the memory data register 44, and then stored in the cache memory via the data line 5. is sent to device 120. In the cache storage device 20, the data sent via the data line 6 is set in the write data register 24, and when the cache memory 21 is updated, it is set in the data register 25 and sent to the calculation unit via the data M6. .

The amount of data written to the cache memory 21 is generally several times the data width of the arithmetic section. This amount is usually determined so that the product of the probability that data exists in cache memory 21 and the processing time required to write data from main storage device 40 to cache memory 21 is small.

The cache storage device 20 shown in FIG.
If 20 were removed, the processing device would become inoperable, so it was impossible to remove all of them.

In order to make the entire cache storage device removable, it is conceivable to adopt the configuration shown in FIG. 2.

In this device, the operation when data exists in the cache memory 21 is exactly the same as that of the device shown in FIG. 1 described above.

If there is no data in the cache memory 21, the check circuit 43 corrects the data sent via the memory data line +, and the data is stored in the memory data line.

At the same time as setting the jista cow hand, data [8t-interval.

Then, the data is sent to the cache storage device 20 and the cache memory 21 is updated. The data set in the memory data register 44 is sent to the arithmetic unit via the data V46. At this time, no data is sent from the data register 26 of the cache storage device 20 to the data 1116.

However, in the device shown in FIG. 2, it is necessary to add a data line 8 for updating the cache memory to the main memory control unit 40 compared to the device shown in FIG. Increased number of wires, L8 engineering and rr 8 I
If the number of modules equipped with multiple modules increases...
However, there were some problems, so it cannot necessarily be said that it is something that should be criticized.

The present invention has been made in view of the above circumstances, and its purpose is to eliminate the above-mentioned problems of conventional cache storage devices and to increase the cost of the basic parts of processing devices. The purpose of the present invention is to provide a flexible cache storage device.

The above-mentioned object of the present invention is to provide memory data with an error correction code that can detect and correct errors that perform data transfer between a processing unit and a main memory control unit in a cache storage device that stores a portion of data in a main memory device. line, an internal data line for transferring read error-corrected data from the main memory to an arithmetic unit in the processing unit, and an address line for indicating all data locations in the main memory; Data is written to the memory data line using data transferred from the processing unit or the main memory, and data read from the cache memory is transferred to the arithmetic unit in the processing unit via all the internal data lines. This is achieved by a cache storage device characterized by:

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the M
'Is the same reference numeral for the same component as shown in J Tsuji's Figures 1 and 2? giving.

The features of the device of this embodiment include the cache storage device 20, the address line 1, the memory data line 4, and the data line 60rb.
It is at the point connected to l.

The fabrication of the device of this embodiment will be explained below. ! (When reading from the main memory, the main memory address sent via the address line 1 is set in the memory address register 46 of the main memory controller 4°.

This address is set in the address register 23 of the cache storage device 20 via memory address [3,
Address array 22. When 0 data to access the cache memory 21 exists in the cache memory 21, the tIC sets the data read from the cache memory 21 in the data register 26 and sends it to the processing unit of the processing device via the data I[6.・:ru. When the data is 1, the data in the memory data register 44 of the main memory control unit 4o is data l.
l64c'rs is not issued.

If there is no data in the cache memory 21,
The main memory control unit 40 instructs the main memory device to read data via the 15 memory address I[3. The above control switching is performed from the cache storage device 2° to the main memory control unit 4.
This is done by the cache presence signal sent to 0. Since the cache presence signal is always "O" when the cache storage device 20 is not attached (when it is removed or set as 1), it is guaranteed that the main storage device will always be accessed. . Data successively output from the main memory device is sent via the memory line A.

In the main memory control unit 4o, the check circuit 43 corrects the data sent via the 1-rememory data 114Yt.

If the data is correct, it is set in the memory data register 44 and sent to the arithmetic unit via the data line 6. At this time, Ki.

From the data register 26 of the Yash storage [120].

No data is sent to data 4I6.

In the cache storage device 20, the memory data line +? The check circuit 43 corrects the data sent from the main memory via the check circuit 43, sets it in the write data register 24, and writes it in the cache memory 21.

When writing to the host t11 device, address 111
1. The main memory address sent as a child valve is sent to the main memory control unit 4.
Set the memory address register 45 to 0. The stone write data sent via the write data line 2 is set in the memory deep register register 1 of the main memory control section 40, and the output total code generation section 42 generates an error correction code. , and sent to the main storage device via memory data Im4.

In the cache storage device 20, when the data indicated by the memory address 113 exists in the cache memory 21, one wire takes in the write data sent via the memory data line 1 and updates the cache memory 21. If it does not exist in the cache memory 21, the cache storage device does not operate.

As described above, according to the present invention, a cache storage device is connected to a memory data line that transfers data between a processing device and a main memory device, and an internal data line that transfers data read from the main memory device to all arithmetic units. and an address line indicating a data position on the main memory, writing to the cache memory is performed by data transferred from the processing unit or the main memory via the memory data line, and data is transferred from the processing unit or the main memory to the cache memory. The data read from the processor is transferred to the arithmetic unit via the internal data MTh. It has a remarkable effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional cache storage device,
FIG. 2 is a diagram showing an example in which the device shown in FIG. 1 is removable, and FIG. 3 is a block diagram of a cache storage device showing an embodiment of the present invention. . 1 near address line, 2+ write data line, 3:) tl memory address line, 4: memory data M, 5.6.8: data line, 7: write data line, 20: cache l1dll
llll device, 21: cache memory, 22 near address array, 23 near address register, 241 write data register, 25: data register, 40: master control unit, 411 memory write data register, 42 = code creation unit, Key 3: Check section, 4 Cow: Memory/data register, 45: Memory/address register 0 Patent applicant
Attorney, Hitachi, Ltd. Patent Attorney Susuki 1) Tori To-So Figure 1 Figure 2 ■ Figure 3

Claims (1)

[Claims] In a cache storage device that stores a portion of data in a main storage device, a memory data line with an error correction code capable of detecting and correcting errors that transfers data between a processing unit and the main storage device, and death,
All error-corrected data is connected to an internal data line for transferring to the arithmetic unit in the processing unit and an address line indicating the data position on the main memory, and writing to the cache memory is performed by the processing using the memory data line. Performed by data transferred from the device itself or the main storage device,
A cache storage device characterized in that data read from the cache storage is transferred to an arithmetic unit in a processing unit via the internal data line.