JPH04352239A - Data processor - Google Patents

Abstract

PURPOSE:To improve the use efficiency of hardware in mounting units by realizing an error correcting circuit which is reduced in connection signal performance among the mounting units and to decrease the hardware quantity by allowing plural control memories to share the error correcting circuit. CONSTITUTION:The data processor is equipped with a data register 2 which holds data with an ECC(error correction code) and an auxiliary data register 6 which can store the data with the ECC. Further, the system is equipped with an error correcting means 7 which refers to the ECC data transferred to the auxiliary data register 6, corrects an error if there is the error, and supplies it to the auxiliary data register 6 and an inspecting means 4 which inspects an error of data in the data register 2; and the ECC data in the data register 2 is transferred to the auxiliary data register 6 in response to the report from the inspecting means 4, and then transferred to the data register 2 after the error of the data with the ECC is corrected.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a data processing device.
In particular, the present invention relates to error correction in a data processing device controlled by a microprogram to which an error correction code is added.

0002

[Background Art] Error correction code technology was originally developed as a technology for correcting errors in signal transmission paths in digital data communications, but it has also been developed as a countermeasure for high reliability requirements in the data processing field, including electronic computers. It is used as a memory device in various data processing equipment. Another means of achieving high reliability is to apply error correction code technology to control storage. Since control memory was proposed by Wilkes, it has been adopted in many data processing devices, and is described in "Micro program memory" by Hussun.
am theory and princepl
es” (Copyright 1962 pren
It is widely known from the literature such as Tice-Hall. Further, a technique for applying an error correction code to control memory is described in Japanese Patent Publication No. 62-027417. This error correction code technology generates an error correction code from original data, stores it in control memory together with the original data, and checks the presence or absence of errors when reading out the data.In the error detection/correction circuit, the data part and the error correction code are It is essential to refer to the section. Therefore, error detection/correction circuits require multiple signal connections.

On the other hand, LSI technology has developed rapidly in recent years, and
The number of gates built into SI has increased dramatically. However, the increase in the number of LSI input/output pins is currently much smaller than the increase in the number of gates due to physical size constraints, and when a circuit that requires a large number of input/output pins is converted into an LSI,
The gates within the LSI could not be used sufficiently, resulting in an LSI that was inefficient in terms of effective use of resources.

0004

[Problems to be Solved by the Invention] The conventional error correction circuit described above uses a large number of signals, so when converting it into an LSI, it had to be placed on the same LSI as the control memory. When an error correction circuit cannot be placed in a control storage LSI due to number control, it is necessary to either not employ an error correction circuit or to use an error correction circuit LSI that uses a small number of gates. Therefore, in the former case, reliability decreases,
The latter had the disadvantage of increasing the amount of gold and the cost. Furthermore, since the conventional error correction circuit has a large number of signal connections, it is necessary to provide the error correction circuit for control storage, making it difficult to reduce the amount of hardware and cost.

Furthermore, in a data processing device incorporating a plurality of control memories, it is necessary to provide an error correction circuit for each control memory due to the above-mentioned restriction on the number of input/output signals of the LSI. This made it difficult to share control memory between devices.

[0006]

[Means for Solving the Problems] A data processing device of the present invention includes a data register that holds data with an error correction code (ECC), an auxiliary data register that can store the data with the ECC, and data in the data register. a first transfer means for transferring the data in the auxiliary data register to the auxiliary data register; a second transfer means for transferring the data in the auxiliary data register to the data register; and an ECC in the auxiliary data register.
an error correction means that refers to the data, corrects the error if an error exists, and supplies the corrected data to the auxiliary data register; and a checking means that checks the data in the data register for errors;
In response to the detection report from the inspection means, the first transfer means transfers the ECC data in the data register to the auxiliary data register, and the error correction means corrects errors in the ECC data after the transfer. and control means for instructing the second transfer means to transfer the data to the data register after correction.

Another data processing device according to the present invention is an ECC
a plurality of data registers for holding data with ECC, a plurality of checking means for checking errors in each data in the plurality of data registers, an auxiliary data register having a data width capable of storing the data with ECC; an error correction circuit that corrects errors in data with ECC in an auxiliary data register and supplies the auxiliary data; and a first transfer means that selects one register from the data registers and transfers the held data to the auxiliary data register. , a second transfer means for selecting one of said data registers from said auxiliary data register and transferring the data therein; and said data register corresponding to said error report signal in response to said error report signal from said checking means. instructing the first transfer means to select and transfer the held data to the auxiliary register, and selectively transfer the data whose errors have been corrected by the error correction circuit from the auxiliary data register to the data register. and a control circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, a control memory 1 stores data and an error correction code (hereinafter referred to as ECC) corresponding to the data as a pair in a storage location addressed by an address register (CAR) 3. The output is sent to the read register (CSR) 2. The read register (CSR) 2 is composed of a group of flip-flops with a shift function, and includes a shift input terminal (SI) and a shift output terminal (SO). Further, the CSR 2 receives the output of the control memory 2 as a parallel input, and supplies the values held by the aforementioned flip-flop group as a parallel output to the arithmetic unit 8, thereby controlling the operation of the arithmetic unit 8. Furthermore, the parallel outputs of the CSR 2 are sent to an error detection circuit 4, where they are checked for errors.

[0010] This error detection method is based on the adopted ECC, for example, if the SEC/DED method is adopted, the
A circuit such as that disclosed in Japanese Patent No. 032821 will be used. When the error detection circuit 4 detects an error, the control circuit 5
Report to. The control circuit 5 responds to this error report signal to the arithmetic unit 8 and the CAR 3 via the signal line 104.
The update of CSR2 is suppressed, and data input from the parallel input terminal of CSR2 is suppressed.

On the other hand, the dashed line in the center of FIG. 1 indicates the boundary of the mounting unit, and it is desirable to select an appropriate form of LSI or printed board as the mounting unit. Control circuit 5 controls the shift functions of CSR 2 and auxiliary data register (AUXR) 6 via control signal 103. AUXR6 is a shift input terminal (SI
) and shift the data in AUXR6 to the data signal line 10.
It is equipped with a shift output terminal (SO) that sends out to the shift input terminal (SI) of CSR2 via AUX
The number of flip-flops in R6 is the same as the number of flip-flops in CSR2, and the structure is such that data held in just the right amount can be exchanged by shift transfer between both registers. Furthermore, AUXR6 is provided with a terminal for inputting and outputting held data in parallel. Via the data path 107, the error correction circuit (EDAC) 7 can refer to the data in all flip-flops of AUXR6 at once. This ED
AC7 is configured to correct errors in ECC data. The specific configuration of EDAC is the adopted ECC.
Depends on the method. For example, if the 1-bit error correction 2-bit error detection (SEC/DED) method is used,
A circuit such as that described in Japanese Patent No. 032821 can be used. The output of EDAC 7 is sent to AUXR via data path 108.
The error correction data is inputted from the parallel input terminals 6 to 6 as error correction data.

[0012] Here, the CSR read from the control memory
A mechanism for detecting and correcting errors when there is an error in the data in 2 will be explained. The output of CSR2 is checked by an error detection circuit 4, which reports the presence of an error to a control circuit 5, which inhibits updating of the states in CAR3 and arithmetic unit 8, and also controls the parallel input of CSR2. Suppresses data input from the terminal. Subsequently, the control circuit 5 connects CSR2 and AUXR6 via the control signal line 103.
Shift instructions are continued to be sent until the data in both registers are exchanged. The error-containing data transferred to AUXR6 has its errors corrected by EDAC7, and is sent to AUXR6. The control circuit 5 instructs to strobe the corrected data from the parallel input terminals via the control line 105. Subsequently, the control circuit 5 connects CSR2 and AUX via the control line 103.
A shift instruction is sent to R6, and the contents of both registers are exchanged via shift data signal lines 101 and 102. As a result, error corrected data is stored in CSR2. At this point, the control circuit 5 restarts the update operation of the parallel input sides of the CAR 3, the arithmetic unit 8, and the CSR 2, which had been inhibited, via the signal line 104. As a result, the data processing device can continue operating as if there were no errors in the data read from the control memory 1.

[0013] Also, in FIG. 1, CSR2 and AUXR
6, data is transferred via the shift data path, but the shift configuration has the disadvantage that the transfer time increases.

FIG. 2 shows a partial data transfer method using selectors as a second embodiment that alleviates the drawbacks of FIG. In FIG. 2, a data register (C2SR
) 10 and the auxiliary data register (A2UXR) 11 are registers that can be partially written (divided into four in the figure), and the selector (S2EL) 12 and selector (S3EL) 13 are registers that can be partially written (divided into four in the figure).
One of the four divided data of R10 and A2UX811 is selected. By using the selectors (S2EL and S3EL) and the partial write function, data transfer between mounting units can be realized faster than a shift operation and with fewer signal lines than transferring all data at once.

According to the configuration of the embodiment shown in FIGS. 1 and 2, it is possible to realize an error correction circuit in which the number of connection signals spanning between mounting units is reduced, and as a result, the number of logic circuits arranged within the mounting unit can be reduced. Since it can be selected flexibly, it has the effect of improving usage efficiency and reducing cost.

FIG. 3 is a block diagram of a data processing device having two control memories, showing a third embodiment of the present invention. In FIG. 3, it is composed of a microprogram-controlled arithmetic mechanism 17, a microprogram-controlled arithmetic mechanism 18, and an error correction mechanism 19, and these three are housed in different mounting units. Furthermore, the arithmetic units 18 and 19 are controlled by microprograms having the same data width, and the method of generating the added error correction code (ECC) is also the same. Moreover, both arithmetic mechanisms can operate in parallel.

Next, the configuration of each mechanism will be explained. The microprogram that controls the arithmetic mechanism 17 uses EC on the original data.
It is stored in the control memory (C3S) 21 in a format with C appended, and the address is specified by the address register (C3AR) 23. EC read from C3S21
Data with C is a flip-flop with shift function (hereinafter F
A data register (abbreviated as F) is configured by a data register (C3S
R) 22, and the output of the C3SR 22 controls the arithmetic unit (E3XU) 28 and is sent to the error detection circuit (E3CK) 24 for error checking. The error checking method follows the adopted ECC method. For example, SEC/
If the DED method is adopted, a circuit such as that disclosed in Japanese Patent Publication No. 62-032821 will be used. The E3CK 24 reports the detected error to the control circuit (C3NT) 25. The control circuit (C3NT) 25 connects C3 via the signal line 114.
In addition to inhibiting the status updates of AR23 and E3XR28, the function of inputting read data from C3S21 in parallel is inhibited, or these inhibitions are canceled. Also, C3NT
25 responds to the error detection signal received from the E3CK 24 and operates a control circuit (CONT
) 41 to send an error correction request signal.

The arithmetic mechanism 18 has a configuration that is a mapping of the arithmetic mechanism 17. That is, the control memory (C4S) 31 is a C3S
21, and the data register (C4SR) 32 corresponds to C3.
SR22, address register (C4AR) 33 is C3
In the AR23, the error check circuit (E4CK) 34 is E3CK.
33 and a control circuit (C4NT) 35 correspond to the C3NT 25, each having corresponding functions and connection relationships.

On the other hand, the error correction mechanism 19 uses the shift data path 111 from the shift output terminal (SO) of the C3S822.
and a shift data path 161 from a shift output terminal (SO) of C4SR32 by a control signal from a control circuit (CONT) 41;
The output of 0 is used as shift input data, and the shift output terminal (S
Shift the output data from C3SR22 through the data path 112 to the shift input terminal (S1) of C3SR22 and C4SR3.
The auxiliary data register (A3UXR) has a terminal that inputs/outputs all bits of data to be supplied to the shift input terminal (S2) of C2 and held in parallel, and is composed of FFs with the same number of bits as C3SR22 and C4SR35.
26, and an error correction circuit (EDAC) that refers to the parallel data output signal of A3UXR26, corrects the error if there is an error, and supplies it to the parallel data input terminal of A3UXR26.
27 and a control circuit (CONT) 41.

The error correction operation of the data processing apparatus shown in FIG. 3 will be explained. The data read from S3S21 to C3SR22 is checked by E3CK24. E3CK24
When detecting an error, it sends an error detection signal to the C3NT25. C3NT25 connects E3X via signal line 114.
In addition to suppressing updates of U28 and E3AR23 and reading from C3S21 to C3SR22, CONT
The error correction request is sent to 41. If CONT41 is processing an error correction request from arithmetic unit 18, C3NT2
The processing for the correction request from No. 5 is made to wait. CONT4
1, if the error correction request is not being processed, the C3NT immediately
CONT41 receives the correction request from C3SR25, causes selector 40 to select shift data path 111 from C3SR22, sends a shift operation instruction to C3SR22 and A3UXR26, and transfers the data containing errors in C3SR22 to A3UXR26. The E3DAC27 is an error correction circuit configured as in Japanese Patent Publication No. 62-032821, and outputs error-corrected data by referring to error data sent via the parallel outputs of the A3UXR26, and outputs error-corrected data to the parallel input terminals of the A3UXR26. supply to CONT
41 instructs A3UXR 26 to store this corrected data, and then instructs A3UXR 26 and C3SR 22 to transfer the error-corrected data to C3SR 22 via shift data path 112. After this, CONT4 is C
3NT25 is notified of the completion of error correction. When C3NT25 receives this completion notification, C3AR23 and E3XU28
, terminates the inhibiting operation for C3SR22. As a result, the arithmetic mechanism 17 can continue operating as if no error had occurred.

On the other hand, if there is an error in the data read from the C4S31 to the C4SR32, each block in the arithmetic unit 18 performs the same operation as the arithmetic unit 17 described above, and the C4NT35 reads the C4AR33, E4XU38, and C4A
Parallel input to R32 is suppressed and an error correction request is sent to CONT41. Upon receiving this error request, CONT41 shifts selector 40 to shift data path 16 from C4SR32.
1, C4SR32 and A3UXR
26 and transfer the data of C4SR32 to A3UXR26.
The error data is corrected using the E3DAC 17 and stored in the A3UXR 26. CONT41 then transfers C from A3UXR26 via shift data path 112.
After transferring the corrected data to 4SR32, C4NT35
A correction completion notice will be sent to. C4NT35 is C4AR3
3. Finish the inhibiting operation for E4XU38 and C4SR32 and restart the operation.

According to the configuration of the invention shown in FIG. 3, the configuration in which one error correction circuit is shared between a plurality of control memories, which requires a small amount of hardware, can be realized by greatly reducing the number of signals between the control memory and the error correction circuit. By realizing this without increasing the number, a low-cost and highly reliable data processing device can be realized.

[0023]

[Effects of the Invention] As explained above, the present invention improves the efficiency of using hardware within a mounting unit by realizing an error correction circuit that reduces connection signal quality across mounting units, and as a result, This has the effect of reducing costs.

Furthermore, since the present invention enables the configuration shown in FIG. 3, it has the effect of reducing the amount of hardware by sharing the error correction circuit between a plurality of control memories.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data processing device of the present invention.

FIG. 2 is an explanatory diagram showing a partial data transfer method.

FIG. 3 is a block diagram of a data processing device of the present invention in which an error correction circuit is shared between a plurality of control memories.

[Explanation of symbols]

1 Control memory 2 Data register (CSR) 3 Address register (CAR) 4 Error detection circuit 5 Control circuit 6 Auxiliary data register 7 Error correction circuit (EDAC) 8 Arithmetic unit

Claims (2)

[Claims] 1. A data register that holds data with an error correction code (ECC), an auxiliary data register capable of storing the data with the ECC, and a first transfer for transferring data in the data register to the auxiliary data register. means, second transfer means for transferring the data in the auxiliary data register to the data register, referring to the ECC data in the auxiliary data register, correcting the error if an error exists, and transmitting the data to the auxiliary data register; an error correcting means for supplying error correction means; a checking means for checking errors in the data in the data register; Transfer to the register, and E after the transfer
A data processing device comprising: control means for instructing the second transfer means to transfer the CC-attached data to the data register after the errors in the CC-attached data are corrected by the error correction means. 2. A plurality of data registers that hold data with ECC, a plurality of checking means for checking errors in each data in the plurality of data registers, and a data width capable of storing the data with ECC. an auxiliary data register, an error correction circuit that corrects errors in data with ECC in the auxiliary data register and supplies the auxiliary data, and selects one register from the data registers and transfers the held data to the auxiliary data register. a first transfer means for selecting one of said data registers from said auxiliary data register and transferring data to be held; and said error report signal in response to an error report signal from said checking means. instructs the first transfer means to select the data register corresponding to the auxiliary data register and transfer the held data to the auxiliary register; A data processing device having a control circuit for selectively transferring data to a register.