CN117724938A - Memory control method - Google Patents

Abstract

The invention provides a control method of a memory, which comprises the steps of executing a read command, acquiring an idle port and ECC state information which can be used for outputting by the memory after reading data, and outputting the ECC state information by using the idle port. The invention can output ECC state information by using the idle port of the memory without setting an independent output port to output ECC state information, thereby reducing the complexity and cost of the device.

Description

Memory control method

Technical Field

The invention relates to the technical field of semiconductors, in particular to a control method of a memory.

Background

Because of the materials and processing reasons of flash memory, errors can occur during read-write operations and storage, ECC (Error Checking and Correcting, error checking and correction) techniques are used to ensure data integrity. The ECC technique uses extra memory space to hold ECC data (or parity bits), in some cases, when writing data, ECC data for a fixed length data segment is calculated and updated; when the data is read, the ECC data is read out to check whether the read data is correct, if errors within the error correction capability range of the ECC algorithm occur, the ECC algorithm can automatically identify the errors and correct the errors, so that the data error rate is reduced, the system can continuously and normally operate, and the safety and the stability of using the flash memory to operate can be greatly improved.

However, the number of ports of the existing flash memory is limited, and how to perform ECC status indication is a problem in the art.

Disclosure of Invention

The invention aims to provide a control method of a memory, which is used for reducing the complexity and the cost of a device.

In order to achieve the above object, the present invention provides a method for controlling a memory, comprising:

executing a read command to read data;

acquiring idle ports and ECC state information of the memory which can be used for output; the method comprises the steps of,

and outputting the ECC state information by using the idle port.

Optionally, the idle port includes at least one of an input/output port, a write protection port, or a shielded external instruction port.

Optionally, the ECC status information is single-bit data, double-bit data, or four-bit data.

Optionally, the number of bits of the ECC status information is less than or equal to the number of the free ports, and the ECC status information is synchronously output by using at least one free port.

Optionally, the number of bits of the ECC status information is greater than the number of the free ports, and the ECC status information is output in a time-sharing manner by using at least one free port.

Optionally, the ECC status information includes at least one of whether an ECC error is detected, a type of the ECC error, a number of bits in which the ECC error is detected, a location in which the ECC error is detected, or a number of times of error correction.

Optionally, the idle port outputs the ECC status information in a push-free output mode or an open-drain output mode.

Optionally, after the reading command is executed, after the chip select signal of the memory jumps to unselected, the idle port is acquired and the ECC status information is output.

Optionally, after the chip select signal jumps to be selected, the idle port stops outputting the ECC status information.

Optionally, the output time of the ECC status information is less than or equal to the unselected time of the chip select signal.

The method for controlling the memory comprises the steps of executing a read command, acquiring an idle port and ECC state information which can be used for outputting by the memory after reading data, and outputting the ECC state information by using the idle port. The invention can output ECC state information by using the idle port of the memory without setting an independent output port to output ECC state information, thereby reducing the complexity and cost of the device.

Drawings

Fig. 1 is a flowchart of a method for controlling a memory according to the present embodiment;

FIG. 2 is a signal timing chart of a control method of a memory according to the present embodiment;

wherein, the reference numerals are as follows:

CSB-chip select signal; CLOCK-CLOCK signal; output time of tV-ECC status information; the tz-idle port stops the delay time of the output.

Detailed Description

Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Fig. 1 is a flowchart of a method for controlling a memory according to the present embodiment. As shown in fig. 1, the control method of the memory includes step S100, step S200, and step S300.

Step S100 is performed to execute the read command to read the data.

Specifically, the memory receives and executes a Read Command (Read Command) to Read data. The ECC data is read at the same time when the data is read, and whether the read data is correct is checked according to the ECC data, and if errors (such as bits containing errors and the like) are detected in the read data, the ECC algorithm can be used for correcting errors. These ECC procedures are all recorded in the ECC status register of the memory for viewing by the user.

In this embodiment, the Memory is a Flash Memory (Flash Memory), for example, may be a Nor Flash or a NAND Flash, but not limited thereto, and may be other memories with ECC functions.

Step S200 is executed to obtain the free ports and ECC status information of the memory available for output.

Specifically, the idle port is a port where the memory is available for output, and is in an idle state at the current time, available for output. For example, the idle port may be an input/output port (SI port or SO port) or a port where an output function is multiplexed with other functions, and the multiplexed port may be, for example, a write protect port (WP port) or a shield external instruction port (HOLD port).

Further, the ECC status information may be single bit data, double bit data, or four bit data.

It is worth noting that the ECC status information may be obtained from the ECC status register of the memory. In some embodiments, the ECC status information includes at least one of whether an ECC error is detected, a type of ECC error, a number of bits in which an ECC error is detected, a location in which an ECC error is detected, or a number of errors.

For example, the ECC status information may be single bit data, where the ECC status information may include only whether an ECC error is detected, for example, when the data stored in the bit is 0, indicating that no ECC error is detected; when the bit stores data of 1, the detection of ECC error is indicated. The ECC status information may also be two-bit data, where the ECC status information may include whether an ECC error is detected and a type of the ECC error, for example, when the two-bit stored data is 00, it indicates that the ECC error is not detected; when the two-bit stored data is 01, the one-bit ECC error is detected and corrected; when the two-bit stored data is 10, characterizing that a two-bit ECC error is detected; when the two bits of stored data is 11, it is characterized that a double program page ECC error is detected. Of course, the above is only an example, the ECC status information may also be represented by four or more bits, at which time the ECC status information may carry more ECC information, which is not illustrated here.

Step S300 is executed, in which the ECC status information is output by using the free port.

Fig. 2 is a signal timing chart of the control method of the memory according to the present embodiment. As shown in fig. 2, in this embodiment, the memory further has a chip select port (CS port) for inputting a chip select signal (CSB signal) and a CLOCK port (CLK port) for inputting a CLOCK signal (CLOCK signal). For example, the chip select signal CSB is selected at a low level, not selected at a high level, and when the chip select signal CSB is at a low level, it indicates that the memory is selected, and the memory enters a working state, and may normally execute a write command, a read command or an erase command under the control of the CLOCK signal CLOCK; when the chip select signal CSB is high, it indicates that the memory is not selected, and the memory enters a standby state.

Further, in this embodiment, after the chip select signal CSB is selected (low level), the read command is executed and the data is read, and then, when the chip select signal CSB transitions to unselected (transitions to high level), the free port is acquired and the ECC status information is output by using the free port. At this time, the ports of the memory available for output are all idle states, any one of the ports can be selected as the idle port to output the ECC state information, the selection scope of the idle port is larger, and the operation of outputting the ECC state information does not adversely affect the normal operation of the memory.

With continued reference to fig. 2, in this embodiment, the ECC status information is four-bit data, and after the chip select signal CSB transitions to a high level, the ECC status information is output in a time-sharing manner by using the SI port, the output time of the ECC status information is tV, and the output time of the ECC status information tV is typically several nanoseconds. Also, in order to avoid that the operation of outputting the ECC status information affects the normal operation of the memory, the output time tV of the ECC status information needs to be less than or equal to the unselected time of the chip select signal CSB.

After the chip select signal CSB transitions to selected, the free port needs to stop outputting the ECC status information, so as not to affect the normal operation of the memory. Of course, due to signal delay, the idle port may need to delay for a certain time tz to stop outputting, but the delay time tz for stopping outputting of the idle port is usually very small, and does not have a great influence on the normal operation of the memory.

Of course, in some embodiments, the read command may be executed and data may be read after the chip select signal CSB is selected (low level), and the spare port may be acquired and the ECC status information may be output by using the spare port after data is read (without waiting for the chip select signal CSB to jump to be unselected). At this time, some ports of the memory may be in a working state, other ports may be in an idle state, and then a port in an idle state is selected from the ports available for output of the memory to output the ECC state information, the output of the ECC state information is more timely and efficient, and the operation of outputting the ECC state information does not adversely affect the normal operation of the memory.

It should be noted that, the number of bits of the ECC status information may be consistent with or inconsistent with the number of the free ports, and when the number of bits of the ECC status information is less than or equal to the number of the free ports, the ECC status information may be synchronously output by using at least one of the free ports; when the number of bits of the ECC status information is greater than the number of free ports, the ECC status information may be time-divisionally output using at least one of the free ports. For example, the ECC status information is 4 bits, where SI port, SO port, WP port, and HOLD port may be selected to output the ECC status information synchronously, SI port outputting the first bit of the ECC status information, SO port outputting the second bit of the ECC status information, WP port outputting the third bit of the ECC status information, HOLD port outputting the fourth bit of the ECC status information; of course, SI port time-sharing output of the ECC status information may be selected, where SI port time-sharing output of the first, second, third, and fourth bits of the ECC status information; alternatively, SI port and SO port may be selected to output the ECC status information in a time-sharing manner, SI port outputs the first bit and the second bit of the ECC status information in a time-sharing manner, and SO port outputs the third bit and the fourth bit of the ECC status information in a time-sharing manner; the above is only an example, but should not be limited thereto.

Further, the idle port may Output the ECC status information in a strong Output manner such as a push-pull Output manner (push-pull Output) or in a weak Output manner such as an open-drain Output manner (open-drain Output). Since some of the idle ports may have Bus multiplexing, in order to avoid interference or collision (collision) with the output of other modules of the memory when the idle ports output the ECC status information, the idle ports preferably output the ECC status information by using a weak output mode.

In summary, the method for controlling a memory according to the embodiment of the present invention includes executing a read command, acquiring an idle port and ECC status information of the memory available for output after reading data, and then outputting the ECC status information using the idle port. The invention can output ECC state information by using the idle port of the memory without setting an independent output port to output ECC state information, thereby reducing the complexity and cost of the device.

It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, the description is relatively simple because of corresponding to the method disclosed in the embodiment, and the relevant points refer to the description of the method section.

It should be further noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.

It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims (10)

1. A method for controlling a memory, comprising:

executing a read command to read data;

acquiring idle ports and ECC state information of the memory which can be used for output; the method comprises the steps of,

and outputting the ECC state information by using the idle port.

2. The method of controlling a memory of claim 1, wherein the idle port comprises at least one of an input/output port, a write protect port, or a mask external instruction port.

3. The method of controlling a memory according to claim 1, wherein the ECC status information is single-bit data, double-bit data, or four-bit data.

4. A method of controlling a memory according to any one of claims 1 to 3, wherein the number of bits of the ECC status information is smaller than or equal to the number of free ports, and the ECC status information is synchronously output using at least one of the free ports.

5. A method of controlling a memory according to any one of claims 1 to 3, wherein the number of bits of the ECC status information is greater than the number of free ports, and the ECC status information is output by time-sharing at least one of the free ports.

6. The method of controlling a memory according to any one of claims 1 to 3, wherein the ECC status information includes at least one of whether an ECC error is detected, a type of the ECC error, a number of bits in which the ECC error is detected, a position in which the ECC error is detected, or the number of error corrections.

7. A method of controlling a memory according to any one of claims 1 to 3, wherein the free port outputs the ECC status information in a push-free output mode or an open-drain output mode.

8. A method of controlling a memory according to any one of claims 1 to 3, wherein after the execution of the read command, the free port is acquired and the ECC status information is output after the chip select signal of the memory jumps to unselected.

9. The method of controlling a memory according to claim 8, wherein the free port stops outputting the ECC status information after the chip select signal transitions to selected.

10. The method of controlling a memory according to claim 8, wherein an output time of the ECC status information is less than or equal to an unselected time of the chip select signal.