JP5201597B2 - Memory initialization circuit, memory initialization method, and information processing apparatus - Google Patents

Description

  The present invention relates to a memory initialization circuit, a memory initialization method, and an information processing apparatus.

  Conventionally, initialization of memory data is performed by writing ECC (Error Correcting Code) and data pattern to all words (Word) in the memory at the time of system startup. It was.

  However, in the conventional memory initialization method, there is a bug in the software, and if the memory read is performed before data is written to the memory, the ECC and data are already correctly written at the time of initialization. Even if the software reads an unwritten word, the hardware (HW) cannot detect a bug, and if the software (SW) does not have a data check description, it remains malfunctioning and no software bug has been found.

  In this regard, Patent Document 1 describes a method of performing memory initialization in parallel using a memory controller of FB-DIMM (Fully Buffered Dual Inline Memory Module). Patent Document 2 describes an apparatus that protects access from different individual identification numbers by using an individual identification number and an error correction code to store converted data in a storage unit.

JP 2008-262325 A Japanese Patent Laid-Open No. 04-310026

  With regard to memory initialization, high speed is required, and Patent Document 1 realizes a high speed function of memory initialization, but does not detect a software bug in hardware (HW). Absent. Further, Patent Document 2 prevents data destruction by encoding data using an individual identification number when writing data, and does not detect software bugs in hardware.

  An object of the present invention is to provide a memory initialization circuit capable of solving the above-described problems and detecting a software bug with hardware.

To achieve the above object, the memory initialization circuit according to the present invention generates initialization data having a specific data pattern, writes the ECC and data in the memory, and initializes the initialization data as the data. Memory initialization control means for controlling the memory initialization operation so as to write data, and means for detecting a software bug by determining the initialization data, wherein the detection means includes an ECC error and the initialization. Further determining which of the errors detected by the data determination has occurred , the memory initialization control means is a memory area used by the software when the operating software releases the memory memory address information that holds the control memory initialization operation to write the initialization data only address using And wherein the Rukoto.

The memory initialization method according to the present invention generates initialization data having a specific data pattern, and initializes the memory so that the initialization data is written as the data when ECC and data are written to the memory for initialization. Control the operation, detect a bug in the software by determining the initialization data, further determine whether an error has occurred between the ECC error and the error detected by the determination of the initialization data , When the internal software releases the memory, the memory initialization operation is performed so that the initialization data is written only to the used address by holding the memory address information of the memory area used by the software. It is characterized by controlling .

  An information processing apparatus according to the present invention includes the memory initialization circuit described above and a memory initialized by the memory initialization circuit.

  According to the present invention, a software bug can be detected by hardware by writing initialization data having a specific data pattern when ECC and data are written to the memory when the memory is initialized.

It is a figure which shows the structure of the principal part of the information processing apparatus provided with the memory initialization circuit which concerns on embodiment of this invention. It is a figure explaining the operation | movement regarding the error detection after the initialization at the time of system starting by the memory initialization circuit shown in FIG. It is a figure explaining the operation | movement regarding the memory initialization after completion | finish of the application in operation by the memory initialization circuit shown in FIG.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 1, an information processing apparatus according to an embodiment of the present invention includes a memory 600 and a memory initialization circuit for initializing the memory 600. The memory initialization circuit includes a memory (MEM) initialization control circuit 100, a memory controller (MEM Controller) 200, a write enable selector 300, a poisoning data generation circuit 400, a write data selector 500, an ECC check (ECC check). ) Circuit 700, address buffer (Address Buffer), address selector 800, address buffer 900, and address selector 1000.

  The memory initialization control circuit 100 receives a memory initialization signal from a diagnostic processor (not shown) or an application end signal from an OS (Operating System) (not shown) and receives a data select signal from the memory initialization control circuit 100. The address select signal and the address select signal of the address buffer 900 are generated.

  The memory controller 200 generates a normal address, write enable, and write data during normal operation.

  The write enable selector 300 selects a memory write enable during normal operation or a memory write enable during initialization using the data select signal as a select signal.

  The poisoned data generation circuit 400 generates poisoned data (hereinafter referred to as “poisoned data”) as initialization data having a specific data pattern when writing ECC and data in the memory 600.

  The write data selector 500 selects write data to the memory 600.

  The ECC check circuit 700 determines an ECC error due to a hardware failure and poisoned data.

  Address buffer address selector 800 selects an input of address buffer 900.

  The address buffer 900 holds an address during normal operation.

  The address selector 1000 selects whether the output of the address buffer 900 is an address during normal operation or an increment address at initialization.

  Next, the operation will be described with reference to FIGS. In the following description, for the sake of convenience, it is assumed that the memory 600 has a c word width of 0 to c-1 words (Word).

  In FIG. 2, Phase 0 indicates a state in which all words in the memory 600 are not initialized before the memory 600 is initialized.

  First, in the initialization phase at the time of system startup in FIG. 2, in the uninitialized phase 0 and the next initialization completion phase 1, the reception of the memory initialization signal from the diagnostic processor before the start of operation is triggered. An operation for initializing all words in the memory 600 from an uninitialized state to a state in which poisoned data is written will be described.

  When the memory initialization control circuit 100 receives a memory initialization signal from the diagnostic processor, the memory initialization control circuit 100 outputs a data select signal, an address buffer address select signal, an address select signal, and a memory initialization write enable signal.

  The write enable selector 300 selects the memory initialization write enable in response to the data select signal and sends it to the memory 600. Also, the write data selector 500 selects the poisoned data generated by the poisoned data generation circuit 400 from the data select signal and sends it to the memory 600.

  In response to an address select signal from the memory initialization control circuit 100, the address selector 1000 selects a +1 increment signal. In the address selector 1000, the address is incremented by +1 every cycle for initializing one word of the memory 600, and by writing up to the word [c-1] of the memory 600, poisoned data is written to all the words of the memory 600, Phase 1 memory initialization is complete.

  Next, an operation for detecting a software bug in phase 2 during operation after phase 1 of completion of initialization at the time of starting the system in FIG. 2 and phase 3 after that will be described. As an example, after data A is written in word [a] of memory 600 in phase 2, the same word [a] in memory 600 is originally read in phase 3 that follows. The case where the word [b] is read will be described.

  First, during phase 2 in operation of FIG. 2, the data select signal from the memory initialization control circuit 100 selects the write enable signal during normal operation by the write enable selector 300 and the normal data by the write data selector 500, respectively. To be sent out.

  Data A is written to the word [a] of the memory 600 by an address during normal operation, a write enable from the memory controller 200 that controls data, write data, and a normal address.

  Next, in phase 3 during operation of FIG. 2, it is assumed that the word [a] in the memory 600 is correctly read, but the word [b] in the memory 600 is read due to a software bug. In this case, since the word [b] in the memory 600 is not written, the poisoned data at the time of memory initialization is written, and the memory read data read from the memory 600 becomes poisoned data. The poisoned data is input to the ECC check circuit 700, and poison detection is asserted.

  The ECC check circuit 700 can discriminate an ECC error and poisoned data caused by a hardware failure other than poisoning. When an unwritten word [b] is read, the ECC check circuit 700 detects a poison, thereby detecting that a read to a word that has not been written has occurred. As a result, the presence of a software bug can be detected in phase 3 of FIG.

  Next, an execution memory space initialization method triggered by the end of application software in operation (hereinafter referred to as “application”) after the memory initialization before the operation start will be described with reference to FIG.

  In the memory initialization before the start of operation, since all words in the memory 600 are poisoned, a software bug is detected for an application executed immediately after the initialization. As the number of poisoned words decreases, the memory space in which errors can be detected decreases. In order to enable error detection as soon as memory initialization, an address buffer 900 that holds an address used by an application in normal operation and an address buffer address selector 800 are provided.

  Here, in the phase 4 and the next phase 5 of the application termination in operation of FIG. 3, after executing the normal application after the memory initialization, before the next application uses the memory space, all the words in the memory 600 are read. A poisoning operation will be described in the same manner as immediately after memory initialization.

  First, it is assumed that four words of words [1, 3, a, b] in the memory 600 have been written in the phase 4 of the application termination in operation of FIG. The address buffer 900 in FIG. 1 receives and holds a normal address from the memory controller 200 during normal operation.

  When the memory initialization control circuit 100 receives the application end signal from the OS, the memory initialization control circuit 100 clears the address buffer address and then sends an address buffer address select signal to the address buffer address selector 800 so as to select +1 increment.

  The address buffer 900 sends only addresses used during operation to the address selector 1000.

  The memory initialization control circuit 100 sends an address select signal to the address selector 1000 so as to select the output of the address buffer 900.

  The address selector 1000 sends the output of the address buffer 900 to the memory 600.

  The write enable selector 300 selects a memory initialization write enable signal according to a data select signal from the memory initialization control circuit 100 and sends the write enable signal to the memory 600.

  The write data selector 500 selects poisoned data according to the data select signal from the memory initialization control circuit 100 and sends it to the memory 600. This operation is performed on word [1, 3, a, b] of memory 600 in steps 1, 2, 3, 4 of the next phase 5 after phase 4 of FIG.

  As described above, after the application is completed, only the written four words are selectively used by the address buffer 900 and the address buffer address selector 800 without initializing all the words in the memory 600, and the phase 5 in FIG. By performing poisoning as in steps 1, 2, 3, and 4, memory initialization can be performed at high speed during operation.

  FIG. 3 illustrates an example in which the memory initialization operation is performed during operation when the application ends, but the memory initialization operation triggered by the process rollout is the same operation.

  As described above, the ECC check circuit 700 can discriminate between an ECC error and a poison error due to a hardware failure. Originally, in the software, the memory data should be referred to after writing. Therefore, when the write sequence is not executed erroneously due to a software bug, poisoned data is read and a poison error is detected. When a poison error is detected, it can be seen that there was a software bug before the corresponding read sequence step.

  As described above, in this embodiment, memory initialization control is performed as means for writing poisoned data (initialized data) having a specific data pattern as data when ECC and data are written at the time of memory initialization. The circuit 100, the poisoned data generation circuit 400, the ECC check circuit 700, and the application end information received from the OS when the application releases the memory 600, and holds the memory address information for the memory area used by the application. An address buffer 900 is included.

  Thereby, the memory initialization circuit according to the present embodiment writes the poisoned data having a specific data pattern as the data when the ECC and data are written into the memory 600 at the time of memory initialization. Software bugs that could not be detected can be detected.

  Further, in this embodiment, in addition to the memory initialization at the time of system startup, when the application releases the memory 600, the application end information is received from the OS, and the memory area used by the application is By having means for holding used address information in the address buffer 900 and writing poisoned data only for the used addresses, the memory 600 can be poisoned at high speed and software bugs can be detected continuously. It is.

  Note that the hardware configuration of the above-described memory initialization circuit is not particularly limited, and any configuration can be applied as long as the functions of the above-described components can be realized.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  By applying the present invention to a memory initialization circuit, a software bug can be detected by a hardware mechanism. In particular, the present invention can be improved in reliability by being applied to an information processing apparatus that requires high reliability.

100 memory initialization control circuit 200 memory controller 300 write enable selector 400 poisoned data generation circuit 500 write data selector 600 memory 700 ECC check circuit 800 address buffer address selector 900 address buffer 1000 address selector

Claims (8)

Memory initialization control means for generating initialization data having a specific data pattern, and controlling the memory initialization operation so that the initialization data is written as the data when ECC and data are written to the memory for initialization. ,
Means for detecting a software bug by determining the initialization data;
The means for detecting further determines whether an error has occurred between an ECC error and an error detected by determining the initialization data,
When the operating software releases the memory, the memory initialization control means holds the memory address information of the memory area used by the software so that only the used address is the initialization data. features and to Rume memory initialization circuit to control the memory initialization operation to write.   2. The memory initialization circuit according to claim 1, wherein the error detected by the initialization data discrimination is an error that a write sequence is not executed erroneously due to a software bug. 3. The memory initialization circuit according to claim 1, wherein the memory initialization control means includes an address buffer that holds memory address information of a memory area used by the software. The memory initialization control means includes
A poisoned data generation circuit for generating poisoned data having a specific data pattern poisoned as the initialization data;
Memory initialization circuit according to any one of claims 1 3, characterized in that it comprises a memory initialization control circuit for controlling the memory initialization operation to write the poison data as said initialization data . Generating initialization data having a specific data pattern, and controlling the memory initialization operation so that the initialization data is written as the data when ECC and data are written to the memory and initialized;
By detecting the initialization data, a software bug is detected,
Further discriminating which of the ECC error and the error detected by the discrimination of the initialization data has occurred;
Furthermore, when the operating software releases the memory, the memory address information of the memory area used by the software is retained, so that the initialization data is written so that only the used address writes the initialization data. features and to Rume Mori initialization method to control the reduction operation. 6. The memory initialization method according to claim 5 , wherein the error detected by the initialization data discrimination is an error that a write sequence is not executed erroneously due to a software bug. Generating poisoned data having a specific data pattern poisoned as the initialization data;
7. The memory initialization method according to claim 5 , wherein a memory initialization operation is controlled so that the poisoned data is written as the initialization data. A memory initialization circuit according to any one of claims 1 to 4 ,
An information processing apparatus comprising: a memory initialized by the memory initialization circuit.

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