JPS61169943A - Stack tracer circuit - Google Patents

Abstract

PURPOSE:To supervise the overlap of an area by the small number of parts by distributing the function of a stack tracer circuit into a circuit for storing an area using a RAM as a memory and a circuit for controlling program execution on the basis of the operation of a stack pointer. CONSTITUTION:The data output of a latch circuit 15 is inhibited through a latch control line 5, data which are the address data of a writable/readable memory 13 are inputted from a stack tracer control part 19 to a latch circuit 16 and the data are latched by the latch circuit 16 through a latch control line 6. The contents of the memory 13 which are obtained through a memory read control line 10 are inputted to the control part 19 through a data I/O line 4. When the input data is '1', the area indicates that the internal RAM of a program evaluating microcomputer 11 is used as a memory. The data reading operation is repeated the whole areas of the memory 13 and the overlap between the area used as a memory and a stack area can be tested by the reading operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application IF) The present invention relates to a stack tracer circuit in a program debugging device for a microcomputer.

(Prior art) A stack tracer circuit is a stack tracer circuit that traces the level (a part of the RAM area and stores the return destination address when executing CA and LL instructions) inside a microcomputer.
This is a circuit that tracks how many CALL commands have been executed. The function of the stack tracer circuit is to inhibit program execution when a preset level of the present invention, which will be described later, is reached.

Normally, R inside the evaluation microcomputer used in program debugging equipment for microcomputers.
There are two types of instructions for AM: instructions to use it as a stack and instructions to use it as memory (RAM).
Furthermore, instructions for use as memory include direct addressing instructions and indirect addressing instructions.

Among these, the indirect addressing instruction is an instruction that accesses the RAM at the address indicated by the contents of the RAM (usually referred to as a register) at the specified address.

Therefore, in order to store the usage status of the internal RAM of the evaluation microcomputer in real time separately in the area used as a stack and the area used as memory, first analyze the instruction to be executed and determine whether the instruction is related to the stack. In the case of instructions, it is necessary to manage how the stack pointer moves and further instruct the evaluation chip to continue or stop program execution based on the value of the stack pointer.

In the case of an instruction to be used as a memory, it is determined whether the instruction is a direct addressing instruction or an indirect addressing instruction, and in the case of a direct addressing instruction, the address is stored as an area used as a memory.

In the case of an indirect addressing instruction, the contents of the RAM inside the specified evaluation microcomputer will be the address used as memory, so the specified RA
If the contents of M are not known, it cannot be stored as an area used as memory.

Therefore, it is necessary to understand how the RAM inside the evaluation microcomputer has changed due to the executed instruction each time the instruction is executed. When executing an indirect addressing instruction, first the specified RAM
The contents are checked, and the address indicated by the contents is then stored as an area used as memory. The above operation must be completed before the execution of the instruction is completed.

(Problem to be Solved by the Invention) However, in the above method, the instruction is analyzed during the instruction execution time, the internal state of the evaluation microcomputer is grasped based on the result, and the specified Storing the contents of the RAM inside the evaluation microcomputer as an address of an area used as a memory is difficult in terms of time and requires a large number of parts, making it complicated.

This invention solves the drawbacks of the prior art described above, and solves the problems of the RAM inside the evaluation microcomputer in real time.
The present invention provides a stack tracer circuit that solves the problems of difficulty in sensing the usage status of the device and complexity due to the large number of components.

(Means for Solving the Problems) The present invention, in a stack tracer circuit, outputs the value of a data pointer representing an address when a RAM inside a program evaluation microcomputer is accessed to the outside of the program evaluation microcomputer. Using a program evaluation microcomputer with an output terminal, R inside the program evaluation microcomputer is
A circuit that stores an area using A as a memory;
A control means is provided for controlling the program by the movement of the stack pointer.

(Function) According to the present invention, since the stack tracer circuit is configured as described above, when the RAM inside the program evaluation microcomputer is accessed, the value of the data pointer representing the address can be changed to the value of the data pointer in the program evaluation microcomputer. The program is stored in a storage circuit for external extraction, and the execution of the program is controlled by the control means by the movement of the stack pointer, thereby eliminating the above-mentioned problem.

(Example) Hereinafter, an example of the stack tracer circuit of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment.

In FIG. 1, first, as seen in a normal program depacking device, an address line 1 and a data bus line 2 are connected between a program storage memory J2 and a program evaluation microcomputer (hereinafter referred to as microcomputer) 11. It is connected.

The address terminal of the writable/readable memory 13 is connected to the output terminal of the latch circuit #515, the output terminal of the latch circuit 16, the input terminal of the latch circuit 17, and the input terminal of the latch circuit 18. The data terminal of this writable/readable memory 13 is connected to the input terminal of the latch circuit 16 and the stack tracer control section 19 through the entire data input/output line 4.

The data terminal of the comparator 14 is connected to the output terminal of the latch circuit 17, and the other data terminal is connected to the output terminal of the latch circuit 18.

The output terminal of the comparator 14 for receiving the comparison result is connected to the stack tracer control section 19 by a comparison result line 21.

The latch circuit 15 is connected to the program evaluation microcomputer 11 via the data pointer line 3. This latch circuit 15 is connected to a stack tracer control section 19 by a latch control line 5, connected to a latch circuit 16 by a latch control line 6, connected to a latch circuit 17 by a latch control line 7, and connected to a latch circuit 18 by a latch control line 6. They are connected by a line 8, a writable/readable memory 13, a memory write control line 9, a memory read control line 10, and a program evaluation microcomputer 11 via an execution control line 20.

Next, the operation will be explained. First, before the program evaluation microcomputer 11 executes a program (instruction), the following circuit is initialized.

That is, the latch control 1s5 is used to inhibit the output of the latch circuit 15. Next, input the initial value of the stack pointer of the program evaluation microcomputer 11 to the latch circuit 16 from the data input/output 4114 of the stack tracer control unit 19, latch the data to the latch circuit 116 using the latch control s6, and then Using the latch control 1117, the output data of the latch circuit $16 is latched into the latch circuit 1117.

Next, the value of the stack pointer for stopping program execution is input to the latch circuit 16 from the data input/output 1s4 of the stack tracer control unit 19, and the latch control w4
After data is latched into the latch circuit 16 using the latch circuit 6, the output data of the latch circuit 16 is latched into the latch circuit 17 using the latch control line 7.

Next, the writable/readable memory 13 is initialized.

In this case, the latch circuit 16 includes the stack tracer control unit 1
9 data input/output $4 writable/readable memory 1
Input the data that becomes the address data in step 3 and control the latch! Data is latched into the latch circuit 16 using JJ6.

In addition, data input/output $4 can be written to/readable from memory 1.
3 initialization data (for example, 0) and uses the memory write control is9 to write/read the write/readable memory 1.
Write the initial value to 3. This writing is performed over the entire area of the writable/readable memory 13.

Next, when the above circuit initialization is completed, the output of the latch circuit 16 is prohibited using the latch control line 6, and data other than the initialization data (for example, After issuing 1), execute the program.

The stack tracer circuit of the present invention, when an instruction to be executed is fetched from the program storage memory 12 to the program evaluation microcomputer 11 through the data bus is2,
The command is analyzed by the stack tracer control unit 19, and the following three types of operations are performed under the control of the stack tracer control unit 19 according to the analysis result.

(1) (Mode 1) Instructions (for example, MO
When executing V RO, A), as shown in FIG. 3 to the latch circuit 15, and then the stack tracer control unit 19 sends the data "1" to the writable/readable memory 13 using the memory write system @ cotton 9 through the common bus! Write through s22.

(2) (Mode 2) When executing an instruction related to the NISTACK, use the latch control $5 to set the value of the data pointer of the program evaluation microcomputer 11 to the data pointer! s
3 to the latch circuit 15, and then
), the latch circuit 1 is connected using the latch control line 7.
The input data from the latch circuit 15 is latched into the latch circuit 17, and the input data from the latch circuit 15 is latched on the latch circuit 1 using the latch control line 8.

Next, comparison N14 is applied to latch circuit 17. Compare the input data from the latch circuit 18 and the comparison result (large, small, etc.)
is the stack tracer control unit 19 through the comparison result line 21.
Enter.

The stack tracer control unit 19 controls the program evaluation microcomputer 11 to continue or stop the execution of the program through the execution control line 20 in accordance with the input comparison result.

(3) (Mode 3): Mode 1. In the case of an instruction other than mode 2 (for example, NoP), no processing is performed and the next instruction is executed.

After the execution of the program is stopped, the area in which the internal RAM of the program evaluation microcomputer 11 is used as memory can be determined by performing the following operation.

That is, after inhibiting the data output of the latch circuit 15 using the latch control line 5, data that becomes the address data of the writable/readable memory 13 is input from the stack tracer control section to the latch circuit 16, and the latch control $6 is activated. data is latched into the latch circuit 16 using

Next, memory read control! 1! Write using J10/
The contents of the readable memory 13 are taken into the stack tracer control unit 19 through the entire data input/output line 4. When this captured data is "1", it indicates that the area is used as memory.

Memory 13 capable of writing/reading the data read operation
Perform for all areas. This read operation allows checking for overlap with the area used as memory and the stack area.

Note that the stack tracer control unit 19 includes an operating device (not shown) such as a keyboard for setting conditions from the outside.
shall be equipped with the following. The data read from the writable/readable memory 13 is displayed on a screen or on a printer.

(Effects of the Invention) As explained above, according to the present invention, the value of the data pointer representing the address when the RAM inside the program evaluation microcomputer is accessed is output to the outside of the program evaluation microcomputer, and the program to be executed is The content is divided into a circuit that stores the area used as memory for the output signal, and a circuit that controls program execution by the movement of the stack pointer, so the program can be executed in real time while the stack area and memory are stored. The overlap with the used area can be monitored.

In addition, program execution can be finely controlled by the value of the stack pointer, and the value of the data pointer is output from the program evaluation microcomputer to the outside of the evaluation microcomputer, so it can be expected that the number of parts will be reduced compared to conventional circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the stack tracer circuit of the present invention, and FIG. FIG. 2 is a block diagram showing the configuration of the main part during operation when executing instructions regarding the stack in the same stack tracer circuit as above. 11...Program evaluation microcomputer, 12... memory for program storage, 13... writable/readable memory, 14... comparator, 15-18... latch circuit,
19...Stack tracer control unit. Figure 2 (a) fbe (b)

Claims (1)

[Claims] A first latch circuit that takes in the value of the data pointer of the program evaluation microcomputer when executing an instruction that uses the RAM inside the program evaluation microcomputer as a memory or when executing a stack-related instruction; a writable/readable memory for writing data latched by the first latch circuit when executing an instruction to use the stack as a memory; a second latch circuit that latches the value of the data pointer, and a stack pointer value that is used to stop program execution when the program evaluation microcomputer is initialized before executing program instructions. a third latch circuit for latching, a comparator for comparing the data latched in the second and third latch circuits when executing an instruction related to the stack, and a comparator for comparing the data latched in the second and third latch circuits when executing an instruction related to the stack; The microcomputer for program evaluation takes in the transferred instruction to be executed and analyzes the case of executing an instruction that uses the RAM as a memory and the case of executing an instruction related to the stack, and based on the comparison result of the comparator. a stack tracer control unit that controls the continuation or abort of the program and, when controlling the abort, reads the contents of the writable/readable memory and determines whether or not the instruction is to use the RAM as a memory; A stack tracer circuit consisting of: