JPH05241650A - Programmable controller - Google Patents

Abstract

PURPOSE:To prevent the destruction of data or the operational defect of programs generated at the time of index modification by tracing data to be set by accessing a data memory using an index register, and verifying the rationality of those data. CONSTITUTION:The program prepared by a program input device 10 is stored through a communication control part 4 into a program memory 1, and upper and lower limit values to the index register are stored in an upper/lower limit value storage part 8 together with an execution address. A program code is read from the memory 1 and transmitted to an instruction detection part 5 by a CPU part 3. When the program code is a write instruction, it is transmitted to a memory control part 6 and a rationality verification part 9 by the instruction detection part 5. The memory control part 6 stores the address, number of times of executing instructions and data value in a trace memory part 7. The rationality verification part 9 reads the execution address and the upper and lower limit values from the upper/lower limit value storage part, collates the transmitted execution address with the data value and reports the result to the CPU part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter referred to as a PC), and more particularly to a programmable controller capable of index-modifying a data memory using an index register.

[0002]

2. Description of the Related Art In general computer technology, it is well known that an index is used as an access method for array variable data, the contents of the index are arbitrarily set, and the array variable is efficiently accessed. .. Even in the PC, access to the data memory by the index modification follows a certain rule, for example, depending on the connection state of the external device such as an input signal from the outside or an output signal to the outside as a calculation result of the control program. A sequence circuit can be created. Further, in recent years, PCs are also equipped with a data processing function in response to the multifunctionalization, and array variables are often handled in the PCs. When handling array variables in a general-purpose computer, it is common to use arbitrary variables as index registers. However, in the PC, a specific variable area of the data memory or a dedicated hardware register is used as an index register,
It controls access to array variables or execution of sequence circuits according to certain rules. FIG. 3 shows an example of a PC index modification program. The example in Figure 3
Input relays 0010-0019 and 0030-0
039, 1000 to 1009 of the output coil is a general operation stop circuit connected to an external device. here,
I = MX0010 is an instruction for setting the content of the variable MX0010 as an initial value in the index register, and is a program for repeatedly executing the operation stop circuit until the content of the index register becomes equal to or more than the content of the variable MX0011. As in this example, a program complying with a certain rule can be efficiently created by modifying the input / output device number or variable data by index modification and programming.

[0003]

However, in programming using such index modification, the program may not operate normally depending on the setting of data in the index register. In the example of FIG. 3, the value of the index register is 0 to 9, but the value of the variable MX0010 for initial value setting or the value of the variable MX0011 for determining the repeating condition causes a malfunction, and the program error. Since it appears as an indirect defect caused by a program error in other parts, it takes a lot of time to investigate the cause. The present invention is a PC capable of preventing data destruction and program malfunction caused by index modification.
The purpose is to provide.

[0004]

The PC of the present invention is a means for arbitrarily setting and inputting the upper and lower limit values of the contents of the index register in accessing the data memory by the index register, and to the index register in the control program. Means for detecting the write command of, the means for storing the number of times of execution of the instruction at the same address, the address, and the contents at the time of execution in response to the detection command, and the means for verifying the validity of the contents at the time of execution. It is characterized by comprising means.

[0005]

According to the present invention, by accessing the data memory using the index register, the data set in the index register is traced, and the rationality of the data is verified, whereby the cause of the malfunction of the PC due to the index modification is eliminated. Can be investigated early.

[0006]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a PC of the present invention. A program memory 1 storing a control program created by a user, a data memory 2 storing input / output data with an external input / output device, and various data during operation of a PC, and a program memory CPU unit 3 that executes in accordance with the contents, a communication control unit 4 that controls communication with the program input device, and a CP
When the U unit 3 fetches an execution instruction from the program memory 1, an instruction detection unit 5 that checks whether the execution instruction is a write instruction to an index register,
In response to the detection command from the instruction detection unit 5, the storage control unit 6 for storing the address of the execution instruction, the number of repeated executions, the initial value, and the updated value, and the above-mentioned instruction execution address,
Upper and lower limit value storage for holding the upper and lower limit values of the index register of an arbitrary execution address set and input from the program input device 10 via the trace memory unit 7 for storing the number of executions, the initial value and the updated value and the communication control unit 4. The rationality verification unit 9 for verifying the rationality of the data value of the index register write command of the execution address by using the value stored in the lower limit value storage unit 8 according to the detection command from the unit 8 and the instruction detection unit 5. Composed of. FIG. 2 shows the program code of the PC of the present invention, and comprises an instruction code section showing the type of instruction, a modification section showing the type of operand that the instruction can take, and the operand section of the instruction. Next,
The operation of the embodiment of the present invention will be described. The program created by the program input device 9 is stored in the program memory 1 via the communication control unit 4, and if the upper and lower limit values are set in the index register, the value is stored in the upper and lower limit value storage unit 7 as an execution address. And also memorize. CPU part 3
Reads the program code stored in the program memory 1, transmits the program code to the instruction detection unit 5, and simultaneously executes it according to the instruction code. The instruction detection unit 5 checks whether the program code transmitted from the CPU unit is a write command to the index register, and if it is not a write command, waits for the next program code to be transmitted from the CPU unit 3. .. If the transmitted program code is an instruction to write to the index register, the execution address and data value of the instruction are transmitted to the storage controller 6. The storage control unit 6 checks whether or not the execution address stored in the trace memory unit 7 is equal to the execution address transmitted from the instruction detection unit 5, and if they are equal, increases the number of executions and stores the transmitted data value in the trace memory. Stored in the unit 7 as an updated value. If they are not equal, the execution address and the data value transmitted from the instruction detection unit 5 are stored in the trace memory unit 7 and the execution count is reset, that is, set to 1. The instruction detection unit 5 transmits the execution address and the data value to the rationality verification unit 9 at the same time as transmitting the storage control unit 6. The rationality verification unit 9 reads the execution address and the upper and lower limit values from the upper and lower limit value storage unit 8 that stores the upper and lower limit values in the index register set and input via the communication control unit 4,
The execution address transmitted from the instruction detection unit 5 is collated, and if it is in the corresponding address range, the data value is further collated with the upper and lower limit set values. As a result of the collation, if the upper and lower limit setting values are exceeded, the CPU unit 3 immediately stops the execution of the subsequent index modification instruction, that is, "NO OPERATIO".
A command for "N" is issued, and the upper and lower limit abnormal states are stored in the trace memory 7. If it is within the upper and lower limit settings, CP
The U unit 3 is caused to cancel the index modification instruction execution stop command, and waits for the next transmission. When the CPU unit 3 receives the instruction to stop the execution of the index modification instruction from the rationality verification unit 9, only the execution of the index modification instruction is stopped.

[0007]

Therefore, according to the present invention, even if the content of the index register deviates from the design value for some reason, the operation is executed by tracing the writing to the index register without affecting the execution operation. There is no need to spend a great deal of time in investigating the cause of defects. Further, in the programming by index modification, the present invention has an effect of preventing the data destruction and the program malfunction caused by the index modification by monitoring the write command to the index register.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PC of the present invention.

FIG. 2 is a diagram showing a program code of a PC.

FIG. 3 is a diagram showing an example of a program for PC index modification.

[Explanation of symbols]

 1 Program Memory 2 Data Memory 3 CPU Section 4 Communication Control Section 5 Command Detection Section 6 Storage Control Section 7 Trace Memory Section 8 Upper and Lower Limit Value Storage Section 9 Rationality Verification Section 10 Program Input Device

Claims (1)

[Claims] 1. A programmable controller having one or more index registers, and an instruction enabling access to a data memory via the index registers, wherein the upper and lower limit values of the contents of the index registers are arbitrarily set. Means for inputting, means for detecting a write command to the index register in the control program, means for storing the number of executions of the instruction at the same address in response to the detection command, the address and the content at the time of execution , A programmable controller characterized by having means for verifying the rationality of the contents at the time of execution.