JPH0836504A - Emulator - Google Patents

Abstract

PURPOSE:To efficiently debug an internal logic circuit of a semi-custom semiconductor device such as a PLD and an FPGA mounted on a application system. CONSTITUTION:Logical description information on the object circuit which is inputted by a user is compiled and transferred to a logic emulation control part 8 and on the basis of the data, logical operation is performed, and the result is outputted to a user interface 13 through a logic bus 12 and outputted to the output pin of a probe 13b connected to the socket for the target PLD of the application system. A slave detecting circuit 5 detects the execution/stop conditions of a logic program, the emulation execution result is traced by a trace memory 6, and the internal logic provided to the application system is efficiently debugged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator,
In particular, PLD (Programmable Logic)
Device), FPGA (Field Program)
The present invention relates to a technique effectively applied to debugging an application system equipped with a semi-custom semiconductor device capable of writing a logic program of a mmable gate array).

[0002]

2. Description of the Related Art According to a study made by the present inventor, an emulator is capable of displaying and changing the contents of a memory while a user program is being executed, and is a main processor of an application device under development by a user. It controls the debugging functions such as input / output signal tracing, program execution, and stop for the microcomputer.

An example of the description of the emulator is "Hitachi Microcomputer Technical Report" published by Hitachi Microcomputer Engineering Co., Ltd.
Issued on the 1st of the month, Volume 2, Issue 2, P21-P22.

[0004]

However, the present inventor has found that the emulator as described above has the following problems.

That is, in recent years, as semi-custom semiconductor devices capable of writing logic programs such as PLDs and FPGAs have spread rapidly and the number of used gates has increased, much of the time for debugging in hardware has been spent in semi-custom semiconductor devices. It has become occupied with debugging.

Therefore, it is difficult for an emulator that emulates only the microcomputer of the application system to efficiently debug the internal logic of the semi-custom semiconductor device mounted in the application system.

An object of the present invention is to provide an emulator which efficiently debugs the internal logic circuit of a semi-custom semiconductor device such as PLD and FPGA mounted in an application system.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the emulator of the present invention is capable of writing a logic program installed in an application system, and emulates a logic emulation control section for performing a logic operation of a semi-custom semiconductor device such as a PLD or FPGA, and a logic emulation. A user interface for converting a signal input / output from the control unit into a predetermined signal is provided, and the logic operation of the PLD is performed by the logic emulation control unit.

In the emulator of the present invention, the execution and stop conditions in the logic program that the logic emulation control section acts on behalf are detected by the break detection circuit that detects the execution and stop conditions of the user program that operates the microcomputer. The execution result of the logic program that the emulation control unit acts on behalf is acquired by the trace memory that acquires the emulation execution result of the user program that operates the microcomputer.

Further, in the emulator of the present invention, the logic emulation control unit receives the logic description data obtained by compiling the logic program and controls the writing of the logic description data, and a logic synthesis block write control block, and the logic synthesis block write. Consists of a logic synthesis block that performs a logical operation according to the logic description written by the control block, a trace that monitors the contents of the logic synthesis block, and transfers data to the break detection circuit and trace memory, and a break controller interface Is.

Also, in the emulator of the present invention, the logic emulation control section is provided with a mode selection section for outputting a selection signal for selecting an operation mode to the logic synthesis block, and the logic synthesis block is rewritable FPGA.
And a plurality of sockets capable of mounting various kinds of semi-custom semiconductor devices in which a logic program is written in advance, and a user arbitrarily selects either the FPGA or the semi-custom semiconductor devices mounted in the plurality of sockets for logic. It is an operation.

[0014]

According to the emulator of the present invention described above, the logic emulation control unit performs the logic operation of the semi-custom semiconductor device, and the user interface converts the signal input / output from the logic emulation control unit into a predetermined signal. The logic operation of the semi-custom semiconductor device can be performed by connecting to the socket in which the semi-custom semiconductor device in the system, the semi-custom semiconductor device such as FPGA is mounted.

Further, according to the emulator of the present invention described above, execution in the logic program which the logic emulation control section acts on behalf of by the break detection circuit,
By detecting the stop condition and acquiring the execution result in the logic program that the logic emulation control unit acts on behalf of the trace memory, it becomes possible to display breaks and traces according to the status in the logic program, and debug the internal logic of the semi-custom semiconductor device. can do.

Further, according to the emulator of the present invention described above, the logic synthesis block write control block receives the logic description data obtained by compiling the logic program, controls the writing of the logic description data, and the logic synthesis block causes the logic synthesis block to be written. Performs a logic operation according to the logic description written by the write control block, and transfers the contents of the logic synthesis block to the break detection circuit and the trace memory by the trace / break control unit interface, thereby performing the logic operation of the semi-custom semiconductor device. And the internal logic of the semi-custom semiconductor device can be debugged.

Further, according to the emulator of the present invention described above, the mode selection unit outputs a signal for selecting a predetermined operation mode to the logic emulation control unit to the logic synthesis block, and a rewritable FPGA, and The user can arbitrarily select any of various kinds of semi-custom semiconductor devices in which the logic program is written, so that debugging can be performed by the actual semi-custom semiconductor device.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of an emulator according to Embodiment 1 of the present invention, FIG. 2 is an internal block diagram of a logic emulation control unit in the emulator according to Embodiment 1 of the present invention, and FIG. FIG. 3 is a block diagram of a logic configuration circuit in the emulator according to the first embodiment of the present invention.

In the first embodiment, the emulator 1 for debugging the application system (not shown) under development by the user
Is provided with a slave microcomputer 2 that substitutes the function of the target microcomputer.

The emulator 1 also includes an emulation controller 3 for controlling the emulation operation, a memory 4 used during the emulation operation, a user program execution, a break detection circuit 5 for detecting a stop condition, and a trace for obtaining an emulation execution result. Memory 6,
A function that acts as a proxy for the logic operation of an emulation memory 7 that can be assigned to any address of the application system and a logic program such as a PLD or FPGA mounted in the application system that can write a logic program. A logic emulation control unit 8 having the above is provided.

Further, the emulator 1 is provided with a user interface 9. The user interface 9 is an interface unit 9 that performs predetermined data conversion.
a and a probe 9b connected to the socket for the target microcomputer of the application system at the tip of the interface 9a.

The slave microcomputer 2 is connected to these emulation control section 3, memory 4, break detection circuit 5, trace memory 6, emulation memory 7, logic emulation control section 8 and user interface 9 via an emulation bus 10. Has been done.

Further, the logic emulation control unit 8
Is connected to the break detection circuit 5 and the trace memory 6 via the monitor bus 11, and can perform a break or a trace display according to the status in the logic program.

Further, the logic emulation control section 8 is connected to the user interface 13 via the logic bus 12. The user interface 13 is also composed of an interface section 13a for performing a predetermined data conversion, and a probe 13b connected to a socket for the target PLD of the application system at the tip of the interface section 13a.

Further, the emulator 1 is provided with a master microcomputer 14 for controlling the emulator 1. The master microcomputer 14 has a system memory 15 as an application system memory and an I / O interface section for performing predetermined data conversion. 16 and the system bus 17 are connected.

Further, the I / O interface section 16 is connected with a CRT 18 for a man-machine interface for inputting / outputting data and a disk 19 for a data memory.

Further, the master microcomputer 14 can access each of the emulation control section 3, the memory 4, the break detection circuit 5, the trace memory 6, the emulation memory 7 and the logic emulation control section 8, and at the time of executing the emulation. The slave microcomputer 2 executes the user program stored in the application system or the emulation memory 7.

Next, the operation of this embodiment will be described.

First, the user selects VHD from the disk 19.
L (VHSIC Hardware Descripti
on Language) to load the logic description information of the target PLD expressed in a description language for logic design.

Then, the logic description information is compiled, and the result of the compilation is transferred to the logic emulation control unit 8 via the system bus 17.

Next, the logic emulation control unit 8
Performs a logical operation based on the transferred data according to the signal state input to the target PLD of the application system, outputs the result to the user interface 13 via the logic bus 12, and outputs the PLD that is the actual chip or F
The PGA is removed and output is made to the output pin of the probe 13b connected to the socket for the target PLD of the application system.

Further, the logic emulation control unit 8
As shown in FIG. 2, a logic synthesis block write control block 20 that receives the logic description data transferred via the system bus 17 and controls the writing of the logic description data is provided inside.

Further, the logic synthesis block write control block 20 outputs to the output pin of the target PLD according to the signal state input to the target PLD in the application system according to the logic description written by the logic synthesis block write control block 20. It is connected to the logic synthesis block 21 via a write control bus 22.

Further, the logic synthesis block 21, the trace,
The break controller interface 23 and the user interface 13 are connected to each other via the logic bus 12.

Further, the trace / break control unit interface 23 monitors the logic bus 12 and sends predetermined data preset by the user via the monitor bus 11 to the break detection circuit 5 (shown in FIG. 1) and the trace. Data is transferred to the memory 6 (shown in FIG. 1).

Therefore, the compiled logic description is sent to the logic emulation control unit 8 via the system bus.
Is transferred to the logical synthesis block write control block 20 and the logical description data is written to the logical synthesis block 21.

Further, as shown in FIG. 3, the inside of the logic synthesis block 21 includes PLDs and FPs with a certain gate scale.
The general-purpose logic synthesizer 21a is composed of a large-scale rewritable FPGA including a GA, and pin assignment is performed according to the device type transmitted together with the logic description data.

When the logic synthesis block write control block 20 writes the logic description in the general-purpose logic synthesis section 21a, the general-purpose logic synthesis section 21a performs a logical operation based on the transferred data and outputs the result to the logic bus 12. To the user interface 13 via the output terminal of the probe 13b connected to the socket for the target PLD.

The execution of the logic program set by the user and the detection of the stop condition are performed by the break detection circuit 5 through the trace monitoring the logic bus 12 and the break controller interface 23. Is also performed by the trace memory 6 via the trace / break control interface 23.

As a result, in the first embodiment, the logic emulation control section 8 operates in the same manner as the target PLD, the operation signal is monitored by the break detection circuit 5 and the emulation memory 6, and the break and the break depending on the status of the logic program are performed. By enabling the trace display, the internal logic of the PLD and FPGA provided in the application system can be efficiently debugged.

(Embodiment 2) FIG. 4 is an internal block diagram of a logic emulation controller in an emulator according to Embodiment 2 of the present invention, and FIG. 5 is a block diagram of a logic configuration circuit in an emulator according to Embodiment 2 of the present invention. is there.

In the second embodiment, a selection signal for selecting an operation mode is provided in the logic emulation block 21 inside the logic emulation control section 8 as shown in FIG.
A mode selection section 24 for outputting the signal is provided via a selection signal line 25.

Further, as shown in FIG. 5, the inside of the logic synthesizing block 21 is designed to enable emulation in a general-purpose logic synthesizing section 21a composed of a rewritable FPGA and a PLD and FPGA of an actual chip. Various actual chip mounting areas (sockets) 21b to 21d that can be mounted according to the type of each package are connected via the logic bus 12, and the PLD and FP in which the logical description is written are written.
The FGA is connected to predetermined sockets in the actual chip mounting areas 21b to 21d to perform a logical operation.

Further, the general-purpose logic synthesis section 21a and the actual chip mounting areas 21b to 21d are selected by the user in advance when the logic synthesis block write control block 20 writes the logic description data. This is performed by the selection signal output from 24.

Then, for example, when the general-purpose logic synthesis unit 21a is selected by the mode selection unit 24, the general-purpose logic synthesis unit 21a performs a logical operation based on the transferred data, and the result is sent via the logic bus 12. It is output to the user interface 13 and output from the output pin of the probe 13b connected to the socket for the target PLD.

Next, for example, the actual chip mounting area 21
When selecting the actual chip mounting area 21b from b to 21d, when the user selects the actual chip mounting area 21b by the CRT 18 in advance, the mode selection unit 24 outputs a predetermined signal to select the actual chip area 21b. To do.

At this time, the user installs the PLD and FPFGA in which the logical description is written in advance on the actual chip mounting area 21b.
Mounted in the socket of the real chip PLD or F
Performs a logical operation by PGA.

As a result, also in the second embodiment, the logic emulation control section 8 operates in the same manner as the target PLD, and the operation signal thereof is used as the break detection circuit 5.
By monitoring with the emulation memory 6 and displaying breaks and traces according to the status of the logic program, the internal logic of the PLD and FPGA provided in the application system can be efficiently debugged.

Further, the actual chip mounting areas 21b to 21d
PLD and FPF with logical description written in advance
By selecting the GA and performing the logical operation, the trace by the actual device becomes possible.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the second embodiment, the actual chip mounting areas 21b to 21d are the actual chips PLD and F.
Although the sockets were mountable according to each package type of PGA, these actual chip mounting areas 21b-2
You may make it add the logic program write function of PLD and FPGA mounted in each of 1d.

[0053]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the logic operation of the semi-custom semiconductor device can be substituted by the logic emulation control section provided in the emulator.

(2) Further, in the present invention, the break detection circuit and the trace memory are used to acquire the execution result of the logic program which the logic emulation control unit acts on behalf, thereby performing a break or trace display of the logic program according to the status. You can

(3) Further, in the present invention, the user arbitrarily selects any of the rewritable FPGA and various semi-custom semiconductor devices in which the logic program is written in advance by the mode selection unit. Debugging by PLD of the actual machine can be performed.

(4) According to the present invention, the above (1)
By (3), it is possible to efficiently debug the internal logic of the semi-custom semiconductor device mounted in the application system.

[Brief description of drawings]

FIG. 1 is a block diagram of an emulator according to a first embodiment of the present invention.

FIG. 2 is an internal block diagram of a logic emulation control unit in the emulator according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a logic configuration circuit in the emulator according to the first embodiment of the present invention.

FIG. 4 is an internal block diagram of a logic emulation control unit in an emulator according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a logic configuration circuit in an emulator according to a second embodiment of the present invention.

[Explanation of symbols]

 1 emulator 2 slave microcomputer 3 emulation control unit 4 memory 5 break detection circuit 6 trace memory 7 emulation memory 8 logic emulation control unit 9 user interface 9a interface unit 9b probe 10 emulation bus 11 monitor bus 12 logic bus 13 user interface 13a interface unit 13b Probe 14 Master microcomputer 15 System memory 16 I / O interface section 17 System bus 18 CRT 19 Disk 20 Logic synthesis block Write control block 21 Logic synthesis block 21a General-purpose logic synthesis section 21b-21d Real chip mounting area (socket) 22 Write control bus 23 Trace / Break Control Interface 24 Mode Selector 2 Selection signal line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Ota 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (4)

[Claims] 1. An emulator for evaluating software and hardware of an application system using a microcomputer, the logic acting on behalf of a logic operation of a semi-custom semiconductor device capable of writing a logic program mounted on the application system. An emulation control unit and a user interface for converting a signal input / output from the logic emulation control unit into a predetermined signal are provided, and the logic operation of the semi-custom semiconductor device is performed by the logic emulation control unit. Emulator to do. 2. The logic emulation control unit detects the execution and stop conditions in the logic program that the logic emulation control unit acts on behalf by a break detection circuit that detects the execution and stop conditions of the user program that operates the microcomputer. 2. The emulator according to claim 1, wherein the execution result in the logic program that is executed by the computer is acquired by a trace memory that acquires the emulation execution result in the user program that operates the microcomputer. 3. The logic emulation control section receives logic description data obtained by compiling a logic program and is written by the logic synthesis block write control block for controlling writing of the logic description data and the logic synthesis block write control block. According to the logic description described above, it comprises a logic synthesis block for performing a logical operation, a trace for monitoring the contents in the logic synthesis block, and a trace for transferring data to the break detection circuit and the trace memory, and a break control interface. The emulator according to claim 1 or 2. 4. The logic emulation control unit is provided with a mode selection unit that outputs a selection signal for selecting an operation mode to the logic synthesis block, the logic synthesis block including a rewritable FPGA and a logic in advance. A plurality of sockets in which various kinds of the semi-custom semiconductor devices in which a program is written can be mounted, and a user arbitrarily selects either the FPGA or the semi-custom semiconductor devices mounted in the plurality of sockets and logic. The emulator according to claim 1, wherein the emulator operates.