JPH10105434A - Emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technique for accurately executing brake condition comparison even when the operation frequency of an emulation processor is high. SOLUTION: An emulator is provided with plural sub-emulation buses 51 and 52 respectively capable of being connected to an emulation bus 55, sorting means 31 and 32 which successively sorts the states of the emulation bus to the plural sub-emulation buses at every bus cycle and pluralbrake condition comparing circuits 10A and 10B which are respectively provided in accordance with the plural sub-emulation buses and capable of judging whether or not the states of the respectively corresponding sub-emulation buses coincide with previously set brake conditions. Then, the operation margin of the brake condition comparing circuit is enlarged so as to attain the adequacy of brake detection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation technique, and a software program that operates on a user system by causing a target program (user program) to be debugged by software to be executed by an emulation processor equivalent to the target processor. The present invention relates to an in-circuit emulator capable of supporting development of a computer.

[0002]

2. Description of the Related Art In the development of microprocessor (microcomputer) application equipment, an in-circuit emulator is used to debug an application system and to evaluate the system in detail. The in-circuit emulator is connected between the host computer for software development and the user system under development,
On behalf of the functions of the microprocessor (target processor) included in the user system, it has a function as a debugger and supports detailed system debugging. In such an emulator, the tip of a cable extended from the main body can be connected to a user system via a plug such as a socket for a target processor, and further, various data and status signals can be transmitted in real time during emulation. Real-time tracing function that samples and stores it in the trace memory section, break function that stops emulation operation substantially, performance measurement such as subroutine measurement and execution time measurement in target program, and emulation every predetermined time It has various debugging functions such as an emulation monitor for monitoring the status.

[0003] As an example of a document describing an emulator, "Everything about microcomputer development (pages 78 to 9)" issued by Dempa Shimbun on June 20, 1989.
5)).

[0004]

When a user system is executed on behalf of a user system by causing an emulation processor to execute a program to be subjected to software debugging, operating the processor at its highest frequency requires the performance of the processor. It is extremely important in analysis. For example, if the target processor operates at 60 MHz, the emulation processor may be used for emulation using an emulation processor having the same function as the target processor.
It is desirable to operate at MHz, and in that case,
It is necessary to be able to accurately compare break conditions, measure performance, and even perform emulation monitoring.

However, as the operating frequency of the processor increases, various debugging operations such as the emulator break condition comparison operation cannot keep up with it.
In the break condition comparison, the performance measurement, and the emulation monitor, information that should be originally acquired from the emulation bus may be lost.

An object of the present invention is to provide a technique for accurately comparing break conditions even when the operating frequency of an emulation processor for executing a target program is high.

Another object of the present invention is to provide a technique for accurately performing a break condition comparison and performance measurement even when the operating frequency of an emulation processor that executes a target program is high.

Another object of the present invention is to provide a technique for accurately performing break condition comparison, performance measurement, and emulation monitoring even when the operating frequency of an emulation processor for executing a target program is high. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a plurality of sub-emulation buses (51, 52) which can be respectively coupled to the emulation bus (55), and distribution means for sequentially allocating the state of the emulation bus to the plurality of sub-emulation buses for each bus cycle. (31, 32)
And a plurality of break condition comparison circuits (1) provided corresponding to each of the plurality of sub-emulation buses and capable of determining whether the state of each corresponding sub-emulation bus matches a preset break condition.
0A, 10B) to form an emulator.

At this time, a break detection circuit (50) for obtaining a logical sum of the plurality of break condition comparison circuits and instructing the emulation processor to stop the execution of the target program based on the logical sum.
Can be provided.

A plurality of performance counter circuits (30A, 30B) are provided corresponding to the plurality of sub-emulation buses, respectively, and the plurality of performance counter circuits monitor the corresponding buses, respectively. It can be configured to perform subroutine measurements and time measurements.

Further, a plurality of emulation monitor circuits (70A, 70B) are provided corresponding to each of the plurality of sub-emulation buses, and the states of the corresponding sub-emulation buses at predetermined time intervals are provided by the plurality of emulation monitor circuits. It can be configured to monitor.

The distributing means is provided corresponding to each of the plurality of sub-emulation buses, latches the state of the emulation bus at a predetermined operation timing, and outputs a plurality of outputs to the corresponding sub-emulation bus. Latch circuit (31, 3
2) and when the number of the latch circuits is n, a clock signal for operating the plurality of latch circuits at a frequency of 1 / n of a bus cycle of the emulation bus and at mutually different timings, A clock forming circuit (20) for forming based on a signal output from the emulation processor,
It can be easily formed.

According to the above means, the distribution means is
The state of the emulation bus is sequentially allocated to a plurality of sub-emulation buses in each bus cycle.
This makes the bus cycle in the sub-emulation bus longer than that in the emulation bus, and the operation in the break condition comparison circuit, performance counter circuit, and emulation monitor circuit provided corresponding to the sub-emulation bus. A margin is enlarged, and emulation of a target program can be performed while an emulation processor that executes the target program is operated at high speed.

[0017]

FIG. 3 shows an example of an in-circuit emulator according to the present invention.

The in-circuit emulator is connected between a host computer for software development and a user system 27 under development.
It has the function of a debugger while substituting the function of the target processor originally installed in the system, and supports detailed system debugging.

A PC interface cable 22 and a pod interface cable 24 are pulled out from the main body 21 of the in-circuit emulator.
Is combined with This PC interface board 23
By being installed in an expansion slot of a personal computer (not shown) or the like, the functions of the personal computer are expanded to function as a host computer for software development.

A connector 30 is provided at the tip of the pod interface cable 24, and the pod interface cable 24 is connected to the emulation pod 26 via the connector 30. Emulation pod 2
The lower surface of 6 is provided with a plurality of pins that can be removably coupled to the target processor mounting socket 29 of the user system 27. The emulation pod 26 is connected to the socket 29 of the user system 27 instead of the target processor that is originally mounted on the user system 27. Although omitted in FIG. 2, the emulation pod 26 has a function equivalent to that of the target processor.
An emulation processor for executing a target program targeted for software debugging is mounted.

In some emulators, an emulation processor is mounted on the emulator main body 21. However, if the operating frequency of the processor is high, the actual transmission of the user system 27 by the signal transmission delay on the pod interface cable 24 may occur. Since the operation may be deviated, in this example, a method in which an emulation processor is mounted on the emulation pod 26 is employed.

From the emulator body 21 to the external probe 2
By connecting the tip of the external probe 28 to an appropriate portion of the user system 27, a signal that does not appear on the processor bus can be taken into the emulator main body 21, and the emulation is performed using the signal. Trigger can be given at the time of.

FIG. 1 shows an example of the configuration of the emulator main body, and FIG. 3 shows operation timings of main parts in the emulator.

An emulation bus 55 is formed in the emulator main body 21. The emulation bus 55 is connected to the processor bus 56 of the emulation processor 100 via the bidirectional buffer 12, the pod interface cable 24, and the bidirectional buffer 11 provided in the emulation pod 26. The processor bus 56 includes an address bus for transmitting an address signal and a data bus for transmitting data, and the emulation bus also includes an address bus and a data bus correspondingly. As a result, address signals output from the emulation processor 100 for memory access and various data exchanged between the emulation processor 100 and the outside thereof for arithmetic processing are also transmitted to the emulation bus 55. .

The emulation processor 100 is mounted on the emulation pod 26 shown in FIG. 2, and a plurality of pins provided on the emulation pod 26
, The function of the target processor originally mounted on the user system 27 is performed. A target program (user program) to be executed by the emulation processor 100 is stored in an emulation RAM (random access memory) 35 coupled to an emulation bus 55 via both buffers 14, and by a memory access from the emulation processor 100. The data is transferred to the emulation processor 100.

The emulation RAM 35 is also connected to the system bus 54, and a memory access from a control processor 90 connected to the system bus via the bidirectional buffer 15 is also enabled. The operation of the emulation RAM 35 is controlled by the bidirectional buffer 1
4 by the memory controller 34 coupled to the emulation bus 55 and to the control processor 90 via the bidirectional buffer 15.

Further, the firmware RAM 37 in which an emulation control program executed by the control processor 90 is stored, the emulation processor 1
00 and a shared RAM 33 that can be accessed from both the control processor 90 and the control processor 90.
They are coupled to the system bus 54 and to the emulation bus 55 via the bidirectional buffer 14. For various information on emulation,
The data is transmitted to the personal computer via the system bus 54 and the PC interface cable 22 or the PC interface board 23 shown in FIG. 2, and is displayed on the CRT display device of the personal computer.

The emulation processor 100
Sub-emulation buses 51 and 52 are provided to enable emulation of a target program in a state where the CPU is operated at a high speed. The sub-emulation buses 51 and 52 are provided with break condition comparison circuits 10A and 10A for break condition comparison. 10B, performance counter circuits 30A and 30B for performance measurement, and emulation monitor circuits 70A and 70B for emulation monitor.

The sub-emulation bus 51 is connected to the emulation bus 55 via the D-type latch circuit 31, and the sub-emulation bus 52 is connected to the emulation bus 55 via the D-type latch circuit 32. Although the D-type latch circuits 31 and 32 are each shown as one logic circuit, actually, the D-type latch circuits 31 and 32 are arranged in a number corresponding to the number of bits constituting the emulation bus 55.

The emulation bus 55 is connected to the data input terminals D of the D-type latch circuits 31, 32. The sub-emulation bus 51 is connected to the output terminal Q of the D-type latch circuit 31, and the sub-emulation bus 52 is
It is coupled to the output terminal Q of the type latch circuit 32. A clock signal for operating the D-type latch circuits 31 and 32 is as follows.
Generated by the clock forming circuit 20.

Although not particularly limited, the clock forming circuit 20 performs non-inversion by dividing the reference timing signal ASETS * (* indicates low active or signal inversion) output from the emulation processor 100 by 1/2. Clock signal CL and inverted clock signal C
Generate L *. The non-inverted clock signal CL is input to the D-type latch circuit 31, the break condition comparison circuit 10A, the performance counter circuit 30A, and the emulation monitor circuit 70A as their operation clocks. The inverted clock signal CL * is output to the D-type latch circuit 32, the break condition comparison circuit 10B, the performance counter circuit 30B, and the emulation monitor circuit 7.
0B are input as their operation clocks. The non-inverted clock signal CL and the inverted clock signal CL *
Is a half frequency of the reference timing signal ASETS * output from the emulation processor 100, and is a signal of a complementary level to each other. Therefore, the D-type latch circuits 31 and 32 whose operations are controlled by such a clock signal alternately latch the state of the emulation bus 55 every bus cycle of the emulation bus 55. For this reason, as shown in FIG.
The state of the emulation bus 55 is determined by the D-type latch circuit 3.
The latch operation of the sub-emulation bus 5 in each bus cycle of the emulation bus 55
1, and 52 are transmitted alternately. Thus, the non-inverted clock signals CL and C output from the clock forming circuit 20
Based on L *, the state of the emulation bus 55
Since the signals are alternately allocated to the sub-emulation buses 51 and 52 for each bus cycle of the emulation bus 55, the bus cycle in each of the sub-emulation buses 51 and 52 is halved compared to that of the emulation bus 55, and a clock forming circuit is provided. In the break condition comparison circuits 10A and 10B, the performance counter circuits 30A and 30B, and the emulation monitor circuits 70A and 70B which are operated in synchronization with the non-inverted clock signals CL and CL * output from the bus 20, one of the bus cycles of the emulation bus 55 is used. In the cycle of / 2, the state of the corresponding sub-emulation buses 51 and 52 can be captured. For this reason, in break condition comparison, performance measurement, and emulation monitor,
Even when it is difficult to obtain information from the emulation bus 55 due to an increase in the operating frequency of the processor, as described above, one bus cycle of the emulation bus 55 is used.
/ 5 emulation bus 5
The emulation can be accurately performed by acquiring information from the first and the second information 52.

The break condition comparison circuit 10A includes a register for setting a break condition, a break condition set in this register, and a sub-emulation bus 51.
And a break condition comparison circuit 10B includes a register for setting a break condition and a break for setting a break condition set in this register. It includes a comparator capable of determining whether the condition and the state of the sub-emulation bus 52 match. The break detection circuit 50 coupled to such a break condition comparison circuit 10A, 10B
A logical sum circuit for calculating the logical sum of the comparison results of A and 10B. In the comparison by the break condition comparing circuit 10A or the break condition comparing circuit 10B, when the state of the sub-emulation bus matches the preset break condition, the break detecting circuit 50 sets the break signal ASEBRK * to low level. Asserted. Then, the break acknowledge signal ASEBRKAK * is asserted to a low level by the emulation processor 100, and the execution of the target program is stopped. Break acknowledge signal ASEBRK
When AK * is asserted to a low level, the runstep generation circuit 36 generates a runstep signal RUNSTEP *.
Is negated to the high level, the bidirectional buffer 13 is turned on, and the system bus 54 is connected to the break condition comparison circuits 10A and 10B, the break detection circuit 50, the performance counter circuits 30A and 30B, the performance control circuit 60, and the emulation monitor circuit 70A. , 70B, and various settings relating to breaks, performance measurement, and emulation monitoring can be performed by the control processor 90. When the run step signal RUNSTEP * is asserted to a low level by the run step generation circuit 36, the bidirectional buffer 13 is turned off and the control processor 90
To break condition comparison circuits 10A and 10B, break detection circuit 50, performance counter circuits 30A and 30
B, access to the performance control circuit 60 and the emulation monitor circuits 70A and 70B are prohibited. Such a state is caused by the emulation processor 1
00 indicates that the target program is being executed, which is a user space. On the other hand, the state in which the execution of the target program by the emulation processor 100 is stopped, the bidirectional buffer 13 is turned on, and various conditions can be set by the control processor 90 and emulation information can be collected is defined as a system space. That is, the break condition comparison, the performance measurement, and the emulation monitor are performed in the user space, and various settings for the same are performed in the system space.

The run step generation circuit 36 has a built-in register 36A for enabling selection of a run state and a step state in order to enable detailed debugging. The setting of the register 36A is performed by the control processor 90. When the step state is set, the target program is continuously executed. When the run state is set, the run step signal RUNSTEP * is executed each time the target program executes one instruction in the emulation processor 100.
Is negated to a high level, and is shifted from the user space to the system space.

Here, the break condition comparison circuits 10A, 1
The setting of the break condition to 0B will be described in detail. The break conditions set in the break condition comparison circuits 10A and 10B are equal to each other.

The break conditions set in the system space where the bidirectional buffer 13 is conductive as described above are not particularly limited, but the first hardware break condition setting, the second hardware break condition setting, and the external probe Break setting by a trigger signal from the CPU 28 and software break condition setting.

In the first hardware break condition setting,
Stop of execution of the target program can be forcibly specified when the specified condition is satisfied (two places). In addition, address and data condition mask specification and two condition satisfaction order specification can be performed. When the target program execution stop is forcibly specified when the specified conditions are satisfied, the values of the address bus and data bus, the value of the program counter, the read / write conditions, the delay / count, and the number of times of passing are specified. You. In the mask specification of the address and the data condition, the address, the program counter, and the data condition can be specified for each bit.

In the second hardware break condition setting,
Stopping execution of the target program can be forcibly specified when the specified conditions are satisfied (up to 24 locations). In addition, the address, data bus value, access type, read / write conditions, and delay count (1 channel) pass count can be specified. (8 channels), an external probe, a system control signal, a negative condition, and the like can be specified. Further, it is possible to specify up to eight conditions to be satisfied and to specify one reset point.

In the software break condition setting, a maximum of 255 places can be set, and the number of passages can be specified.

Next, the performance counter circuit 30
A, 30B and the performance function realized by the performance control circuit 60 will be described in detail.

The performance function enables subroutine measurement and execution time measurement in the target program. Here, the subroutine measurement includes measurement of the number of executions of the subroutine, the number of accesses to the designated area in the subroutine, the number of accesses to the lower subroutine (child) read from the upper subroutine (parent), and the like. In the execution time measurement, the program execution time measurement (GO to POINT time) from the address of the target program executed by designating the execution start address of the target program to the address where the designated condition is satisfied, the first designation The program execution time measurement (POINT to POINT time) from the address where the condition is satisfied to the address where the second designated condition is satisfied, and the execution time integration (POINT to POINT time integration) are included.
In this performance measurement, 20 ns and 250 ns
The accuracy of the time measurement can be specified, such as ns, 1 μS, etc. The maximum number of execution measurements is 65535. Such performance measurement is performed by the performance counter circuits 30A and 30B, and the measurement operation is controlled by the performance control circuit 60.

Further, the emulation monitor 70A,
The emulation monitoring function implemented by the sub-emulation buses 51 and 52 every predetermined time immediately after the execution of the target program is started.
Is monitored, and the monitoring result can be obtained. Specifically, by monitoring the address bus in the emulation bus, an address is acquired from the sub-emulation bus at a rate of, for example, once every 200 ms. The obtained address information is transmitted to the personal computer via the system bus 54 and the PC interface cable 22 and the PC interface board 23 shown in FIG. 2 as information indicating the current execution status of the target program by the emulation processor 100. The information is displayed on the CRT display device of the personal computer.

According to the above example, the following functions and effects can be obtained.

(1) The state of the emulation bus 55 is changed based on the non-inverted clock signals CL and CL * output from the clock forming circuit 20.
Every 5 bus cycles, the sub-emulation bus 51,
52, the bus cycle in each of the sub-emulation buses 51 and 52 is
It is １ ／ compared to that of the emulation bus 55. Therefore, in the break condition comparison circuits 10A and 10B operated based on the non-inverted clock signals CL and CL * output from the clock forming circuit 20, the corresponding sub-circuits are １ ／ of the bus cycle of the emulation bus 55. The state of the emulation buses 51 and 52 can be captured. Therefore, even when the operating frequency of the processor becomes high and it is difficult to obtain address information or data for the break condition comparison from the emulation bus 55, as described above, one half of the bus cycle of the emulation bus 55 is used. By acquiring information from the sub-emulation buses 51 and 52 which are set as a cycle, break detection can be accurately performed.
That is, the state of the emulation bus 55 is sequentially distributed to the sub-emulation buses 51 and 52 for each bus cycle, so that the break condition comparison circuits 10A and 1 provided for the sub-emulation bus are provided.
The operation margin of 0B is expanded, so that even when the processor operates at high speed, break detection can be accurately performed.

(2) Since the state of the emulation bus 55 is sequentially distributed to a plurality of sub-emulation buses in each bus cycle, the operation of the performance counter circuits 30A and 30B provided corresponding to the sub-emulation bus is performed. Since the margin is expanded, the performance can be measured accurately even when the processor operates at high speed. (3) The state of the emulation bus 55 is sequentially distributed to a plurality of sub-emulation buses 51 and 52 for each bus cycle. Accordingly, the operation margin of the emulation monitor provided corresponding to the sub-emulation bus is expanded, so that the emulation monitor can be accurately performed even when the target processor operates at high speed.

(4) The distributing means is provided corresponding to each of the plurality of sub-emulation buses 51 and 52. The distributing means latches the state of the emulation bus 55 at a predetermined operation timing, and also corresponds to each of the corresponding sub-emulation buses. When the number of latch circuits 31 and 32 that can be output to the emulation bus is n and the number of the latch circuits 31 and 32 is n, the plurality of latch circuits are operated at a frequency of 1 / n of a bus cycle of the emulation bus, and A clock signal for operating at mutually different timings can be easily formed from the clock forming circuit 20 for forming based on the signal output from the emulation processor.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, in the above example, the reference timing signal AS output from the emulation processor 100
The non-inverted clock signal CL and the inverted clock signal CL * are generated by taking ETS * into the clock forming circuit 20 and dividing the frequency. However, instead of the reference timing signal ASETS *, the emulation bus 5 is used.
5, the non-inverted clock signal CL and the inverted clock signal CL * are generated based on an address signal or a strobe signal indicating validity of data, a memory read / write instruction signal, and the like. Is also good.

In the above example, as shown by 51 and 52 in FIG. 1, two sub-emulation buses are formed, and the break condition comparison circuits 10A and
10B, a break detection circuit 50, and performance counter circuits 30A and 30B are provided, but three or more sub-emulation buses are formed, and a break condition comparison circuit, a performance counter circuit,
And an emulation monitor circuit may be provided. In this case, a latch circuit (corresponding to 31 and 32 in FIG. 1) is provided for each sub-emulation bus. When the number of latch circuits is represented by n, the frequency is 1 / n of the bus cycle of the emulation bus 55. so,
In addition, the operations of the plurality of latch circuits are controlled at mutually different timings. As the number of sub-emulation buses and break condition comparison circuits provided for the respective sub-emulation buses increases, the bus cycle of each sub-emulation bus decreases as compared with that of the emulation bus 55.
It is possible to support a faster processor.

In the above example, the real-time tracing for sequentially tracing and storing data and address signals and control information applied to the bus is omitted, but the break condition comparison circuits 10A and 10B, the break detection Circuit 50, performance counter circuit 30
Similarly to A and 30B, real-time trace circuits for sequentially tracing and storing data and address signals applied to the bus and control information may be provided for each of the sub-emulation buses 51 and 52. . Further, the emulation processor 100
Is stored in a memory, and a coverage trace circuit that enables the execution address to be grasped by determining the contents of the memory at the end of the emulation is provided in the same manner as the real-time trace circuit. 52 may be provided correspondingly.

In the above description, the case where the invention made by the present inventor is mainly applied to an in-circuit emulator having an emulation pod, which is a field of use, has been described, but the present invention is not limited to this. Instead, by acquiring information on the emulation bus, it can be applied to various systems that support the development of target programs.

The present invention can be applied on condition that at least an emulation bus is coupled to the emulation processor.

[0052]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the state of the emulation bus is sequentially distributed to a plurality of sub-emulation buses in each bus cycle, so that the operation margin of the break condition comparison circuit provided corresponding to the sub-emulation bus is expanded. Even when the target processor operates at a high speed, break detection can be accurately performed.

Further, since the state of the emulation bus is sequentially distributed to a plurality of sub-emulation buses in each bus cycle, the operation margin of the performance counter circuit provided corresponding to the sub-emulation bus is expanded. Even when the processor is operated at high speed, performance measurement can be accurately performed.

Further, since the state of the emulation bus is sequentially distributed to a plurality of sub-emulation buses in each bus cycle, the operation margin of the emulation monitor provided corresponding to the sub-emulation bus is expanded. Even when the processor operates at a high speed, the emulation monitor can be accurately performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an emulator according to an embodiment of the present invention.

FIG. 2 is an external perspective view of the emulator.

FIG. 3 is a timing chart for explaining a main operation of the emulator.

[Explanation of symbols]

 10A, 10B Break condition comparison circuit 20 Clock formation circuit 21 Emulator main body 22 PC interface cable 23 PC interface board 24 Pod interface cable 26 Emulation pod 27 User system 30A, 30B Performance counter circuit 36 Run step generation circuit 50 Break detection circuit 60 Performance control Circuit 70A, 70B Emulation monitor circuit 90 Control processor 100 Emulation processor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideya Fujita 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Tatsuya Suzuki 5, Josuihoncho, Kodaira-shi, Tokyo No. 22-1, Hitachi Microcomputer System Co., Ltd.

Claims (5)

[Claims] An emulation bus coupled to an emulation processor that executes a target program, and an emulator that supports the development of the target program by acquiring information on the emulation bus can be coupled to the emulation bus. A plurality of sub-emulation buses, a distribution means for sequentially allocating the state of the emulation bus to the plurality of sub-emulation buses for each bus cycle, and a plurality of sub-emulation buses provided corresponding to each of the plurality of sub-emulation buses. A plurality of break condition comparison circuits capable of determining whether or not the state of the sub-emulation bus to be executed matches a preset break condition. 2. A break detection circuit for calculating a logical sum of comparison results of the plurality of break condition comparison circuits and instructing the emulation processor to stop execution of a target program based on the logical sum. The emulator according to item 1. 3. A plurality of performance counter circuits provided corresponding to each of the plurality of sub-emulation buses and monitoring the corresponding buses to perform subroutine measurement and time measurement of the target program. 3. The emulator according to 1 or 2. 4. The apparatus according to claim 1, further comprising a plurality of emulation monitor circuits provided corresponding to each of said plurality of sub-emulation buses and monitoring a state of each of said plurality of sub-emulation buses at predetermined time intervals. An emulator according to any one of the preceding claims. 5. The distributing means is provided for each of the plurality of sub-emulation buses, latches the state of the emulation bus at a predetermined operation timing, and can output to the corresponding sub-emulation bus. When the number of the latch circuits is n, the number of the latch circuits is 1 / ラ ッ チ of the bus cycle of the emulation bus.
5. A clock forming circuit for forming a clock signal for operating at a frequency of n and at mutually different timings based on a signal output from the emulation processor. An emulator according to claim 1.