JP3545480B2 - emulator - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to an emulator, and more particularly to a technique effective when applied to system debugging in an application system in which two or more microcomputers are used.
[0002]
[Prior art]
According to the study by the present inventor, debugging in a so-called multi-CPU type application system in which two or more microcomputers are used in an application system being developed by a user is, for example, two sets of microcomputers. In the case of an application system using a microcomputer, two emulators are used.
[0003]
An example of this type of emulator in detail is "E7000 SH7032 SH7034 Emulator User's Manual" issued by Hitachi, Ltd., July 1993.
[0004]
[Problems to be solved by the invention]
However, the inventor of the present invention has found that the following problems are encountered in debugging the emulator in the multi-CPU application system as described above.
[0005]
That is, when an application system in the multi-CPU system is emulated by a plurality of emulators, since the same bus is used, a capacitive load increases at a high speed operation, and the high speed operation tends to be difficult. Yes, there is a risk that the delay will be long.
[0006]
Also, by using a plurality of emulators, it is difficult to share the built-in functions of the emulator with a simple interface.
[0007]
An object of the present invention is to provide an emulator which can perform emulation in a multi-CPU type application system using a plurality of microcomputers by one emulator.
[0008]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
That is, in the emulator of the present invention, a single emulator is provided with a number of slave microcomputers that substitute for the functions of the microcomputer provided in the application system and the number of slave microcomputers corresponding to the plurality of microcomputers. Is what you do.
[0011]
Further, the emulator of the present invention selects either the first clock signal output from the application system or the second clock signal output from the emulator based on the first control signal, and sets the plurality of slave microcontrollers. A clock selecting and supplying means for supplying a clock signal synchronized with the computer is provided.
[0012]
Further, the emulator of the present invention generates a first reset signal based on the second control signal, and resets the plurality of slave microcomputers with the first reset signal or the second reset signal output from the application system. Reset signal output means for selecting one of the signals and outputting the signal to each reset signal input section of the plurality of slave microcomputers to reset the plurality of slave microcomputers is provided.
[0013]
Further, the emulator of the present invention is capable of simultaneously synchronizing trace data and coverage data by inputting a data acquisition signal synchronized with a tracing means for sampling and tracing various data and status signals and a coverage means for displaying an execution address. And data acquisition signal means for acquiring data.
[0014]
[Action]
According to the emulator of the present invention described above, a single emulator is provided with a number of slave microcomputers for performing the functions of the microcomputer provided in the application system in a number corresponding to the plurality of microcomputers. Since a plurality of matching emulators are not required, the number of user interfaces and transmission lines can be reduced, and the capacitive load can be reduced, so that high-speed operation emulation can be realized.
[0015]
Further, according to the emulator of the present invention described above, either the first clock signal output from the application system or the second clock signal output from the emulator is selected based on the first control signal, and The clock selection supply means for supplying a clock signal to the slave microcomputer can supply a clock signal synchronized from the emulator itself to a plurality of slave microcomputers with a simple circuit configuration.
[0016]
Further, according to the emulator of the present invention described above, the first reset signal is generated based on the second control signal, and the first reset signal for resetting the plurality of slave microcomputers or the second reset signal output from the application system. Reset signal output means for selecting one of the two reset signals and outputting the reset signal to the reset signal input section of each of the plurality of slave microcomputers, and outputting a reset signal synchronized from the emulator itself to the plurality of slave microcomputers. be able to.
[0017]
According to the emulator of the present invention described above, the data acquisition signal means for inputting a data acquisition signal synchronized with the tracing means for sampling and tracing various data and status signals, and the coverage means for displaying the execution address, Data acquisition of trace data and coverage data can be performed simultaneously.
[0018]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0019]
(Example 1)
FIG. 1 is a connection diagram between an emulator according to the first embodiment of the present invention and an application system, FIG. 2 is a block diagram of a main part of the emulator according to the first embodiment of the present invention, and FIG. 3 is an emulator according to the first embodiment of the present invention. 3 is a circuit diagram of a clock oscillation circuit and a reset circuit in FIG.
[0020]
In the first embodiment, an emulator 3 for debugging software and hardware is provided between an application system 1 provided with a plurality of microcomputers being developed by a user and a personal computer 2 which is a parent computer for software development. Are connected by predetermined cables CA1 and CA2.
[0021]
Here, in this embodiment, the application system 1 is of a two-CPU type provided with two microcomputers (not shown).
[0022]
The emulator 3 is divided into an emulator unit 3a that is not involved in the application of AS (Application Specific) such as a portion supporting a CPU core of a microcomputer, and a target probe 3b that changes due to the use of an AS such as a pseudo circuit of peripheral functions. The emulator unit 3a and the target probe 3b are also connected by a predetermined cable CA3.
[0023]
Further, the emulator unit 3a sets a master microcomputer for controlling the emulator, a serial interface unit for performing data communication with the personal computer 2, a program execution, and a stop condition for tracing, and stops the program or trace when the condition is satisfied. It is configured by a circuit (not shown) such as a breakpoint control unit.
[0024]
As shown in FIG. 2, the target probe 3b includes a slave microcomputer (hereinafter, slave microcomputer) 4 for performing the function of a target microcomputer which is one of the two microcomputers, and the other microcomputer. The slave microcomputer 5 which performs the function of the target microcomputer is provided.
[0025]
Further, the target probe 3b includes an emulation memory as a rental memory, a control circuit 6 for realizing emulation and various debugging functions, and a socket (not shown) for a target microcomputer in the application system 1 (shown in FIG. 1). A user interface 7 to which the cable CA2 provided at the end is connected is provided.
[0026]
In the target probe 3b, the slave microcomputers 4 and 5, the control circuit 6, and the user interface 7 are connected by a common data bus 8 and address bus 9, respectively.
[0027]
Further, input / output of control signals between the slave microcomputer 4, the control circuit 6, and the user interface 7 is performed via a dedicated control signal bus 10, and the control signal is input / output between the slave microcomputer 5, the control circuit 6, and the user interface 7. Input and output of control signals are also performed via a dedicated control signal bus 11.
[0028]
Further, a data bus buffer 12, an address bus buffer 13, and a control signal are provided between the control circuit 6 and the slave microcomputers 4 and 5 and the user interface 7 for timing the operation speed of each input / output signal. A bus buffer 14 and a control signal bus buffer 15 are provided.
[0029]
Further, between the target probe 3b and the application system 1 (shown in FIG. 1), control signals, address signals, and data signals are input / output via the user interface 7.
[0030]
Then, the software and hardware of the application system 1 are debugged by the connection shown in FIG. 1. When emulating the application system 1 of the 2 CPU system in the present embodiment, the functions of the target microcomputer are assigned to the target probe 3b. The provision of the substitute slave microcomputers 4 and 5 enables emulation by one emulator 3.
[0031]
Further, since the data bus 8 and the address bus 9 can be used in common, only one user interface 7 is required, and the transmission line can be shortened, so that high-speed operation emulation can be realized.
[0032]
The target probe 3b is provided with slave microcomputers 4 and 5 in a number corresponding to the microcomputers (not shown) provided in the application system 1. For example, although three microcomputers are provided, In the application system (not shown), three slave microcomputers are provided in the target probe (not shown).
[0033]
Further, as shown in FIG. 3, the target probe 3b includes a clock oscillation circuit (clock selection supply means) 16 for outputting a second clock signal for operating the slave microcomputers 4 and 5, and the slave microcomputers 4 and 5. A reset circuit (reset signal output means) 17 for outputting a first reset signal for resetting is provided.
[0034]
The clock oscillation circuit 16 includes an oscillator 16a that outputs a second clock signal having a predetermined frequency, an inverter Iv1 that inverts a signal, AND circuits 16b and 16c that are AND circuits, and an OR circuit 16d that is an OR circuit. It is configured.
[0035]
The oscillator 16a is connected to the input of the inverter Iv1, the output of the inverter Iv1 is connected to one input of the AND circuit 16b, and the other is the second clock output from the oscillator 16a in the control circuit 6. A selection signal output unit (not shown) for outputting a first control signal indicating whether to use a signal or a first clock signal output from an oscillator (not shown) provided in the application system 1 ) And connected.
[0036]
The selection signal output unit is also connected to one input of the AND circuit 16c, and the other input is a first clock signal output from the oscillator provided in the application system 1 described above. .
[0037]
Further, the output units of the AND circuits 16b and 16c are connected to the input unit of the OR circuit 16d, and the output of the OR circuit 16d is connected to the respective clock input terminals Ck of the slave microcomputers 4 and 5. .
[0038]
Here, a case will be described in which the clock oscillation circuit 16 uses the oscillator provided in the application system 1.
[0039]
To use the oscillator provided in the application system 1 (shown in FIG. 1), for example, a user inputs a command for selecting the oscillator provided in the application system 1 by the personal computer 2.
[0040]
Then, a predetermined signal is output from the personal computer 2 in response to the command, and a Hi signal, which is a first control signal, is output from a selection signal output unit provided in the control circuit 6 based on the signal.
[0041]
The Hi signal is input to the input section of the inverter Iv1 and one input section of the AND circuit 16c, and the Hi signal input to the inverter Iv1 is inverted to become a Lo signal and input to the other input section of the AND circuit 16b. .
[0042]
Therefore, the second clock signal output from the oscillator 16a provided in the target probe 3b is input to one input portion of the AND circuit 16b, and the Lo signal is input to the other input portion. The output of 16b is a Lo signal.
[0043]
On the other hand, the Hi signal is input to one input of the AND circuit 16c, and the first clock signal output from the oscillator provided in the application system 1 is input to the other input of the AND circuit 16c. The signal synchronized with the signal is output from the output section of the AND circuit 16c.
[0044]
The output of each of the AND circuits 16b and 16c is input to one input of an OR circuit 16d provided at the subsequent stage, so that the clock input terminals Ck of the slave microcomputers 4 and 5 are connected to the application system 1. The first clock signal output from the provided oscillator is supplied.
[0045]
Similarly, to supply the second clock signal output from the oscillator 16a, the user inputs a command to use the oscillator 16a by the personal computer 2, and a predetermined signal is output from the personal computer 2, The Lo signal is output from a selection signal output unit provided in the control circuit 6 based on the signal.
[0046]
The other input of the AND circuit 16b becomes a Hi signal by the signal inverted by the inverter Iv1, and a signal synchronized with the oscillator 16a is output from the output of the AND circuit 16b.
[0047]
The output of the AND circuit 16c is a Lo signal because one input portion is a Lo signal.
[0048]
Since the outputs of the AND circuits 16b and 16c are input to the OR circuit 16d, the clock input terminals Ck of the slave microcomputers 4 and 5 are supplied with the second clock signal output from the oscillator 16a. Become.
[0049]
Thereby, not only the first clock signal output from the oscillator provided in the application system 1 but also the second clock signal output from the oscillator 16a provided in the target probe 3b can be supplied.
[0050]
Next, the reset circuit 17 includes inverters Iv2 to Iv7 for inverting signals and OR circuits 16e and 16f as OR circuits.
[0051]
The input units of the inverters Iv3 and Iv5 are connected so that the second reset signal output from the application system 1 (shown in FIG. 1) is input. The input units of the inverters Iv2 and Iv4 have, for example, , And a second control signal output from the control circuit 6.
[0052]
The outputs of the inverters Iv2 and Iv3 are connected to the respective inputs of the OR circuit 16e, the outputs of the inverters Iv4 and Iv5 are connected to the respective inputs of the OR circuit 16f, and the outputs of the OR circuits 16e and 16f. Are connected to the input portions of the inverters Iv6 and IV7, and the output portions are connected to the reset signal input terminals R of the slave microcomputers 4 and 5.
[0053]
Further, in the present embodiment, the slave microcomputers 4 and 5 are reset by a Lo signal, that is, are set to be active "L".
[0054]
Here, a case where the slave microcomputers 4 and 5 are reset by the second reset signal output from the application system 1 will be described.
[0055]
First, the user inputs a command for resetting the slave microcomputers 4 and 5 with the second reset signal output from the application system 1 by the personal computer 2.
[0056]
In response to the command, the personal computer 2 outputs a second control signal to the control circuit 6, and based on the signal, the control circuit 6 outputs a Hi signal as a second control signal when the slave microcomputers 4 and 5 are reset.
[0057]
In addition, when the slave microcomputers 4 and 5 are reset, when the Lo signal, which is the second reset signal output from the application system 1, is input to the input units of the inverters Iv3 and IV5, the Lo signal is inverted to Hi. A signal is input to each input unit of the OR circuits 16e and 16f.
[0058]
Further, a Hi signal, which is a second control signal output from the control signal 6, is input to the inverters Iv2 and Iv4 input sections, and the Hi signal is inverted and applied to one input section of the OR circuits 16e and 16f. Is entered.
[0059]
As a result, one input of the OR circuits 16e and 16f becomes a Lo signal and the other input becomes a Hi signal, so that the output becomes a Hi signal. However, the signal is inverted by the inverters Iv6 and Iv7 connected to the subsequent stage. Then, the Lo signal is output, and the second reset signal is input to the reset signal input terminals R of the slave microcomputers 4 and 5.
[0060]
Next, a case where the slave microcomputers 4 and 5 are reset by the first reset signal output from the reset circuit 17 will be described.
[0061]
First, the user inputs a command for resetting the slave microcomputers 4 and 5 by the first reset signal output from the reset circuit 17 by the personal computer 2.
[0062]
In response to the command, the personal computer 2 outputs a predetermined signal to the control circuit 6, and based on the signal, the control circuit 6 outputs a Lo signal as a second control signal when the slave microcomputers 4, 5 are reset.
[0063]
Further, when the Lo signal, which is the second control signal, is input from the control circuit 6 to the input portions of the inverters Iv3 and IV5 when the slave microcomputers 4 and 5 are reset, the Lo signal is inverted to become a Hi signal. And input to respective input sections of the OR circuits 16e and 16f.
[0064]
Here, a Hi signal, which is a second reset signal output from the application system, is input to the inverters Iv2 and Iv4 inputs, and the Hi signal is inverted and applied to the other inputs of the OR circuits 16e and 16f. Is entered.
[0065]
As a result, one input of the OR circuits 16e and 16f becomes a Hi signal and the other input becomes a Lo signal, so that the output becomes a Hi signal. However, the signal is inverted by the inverters Iv6 and Iv7 connected to the subsequent stage. Then, the Lo signal is output, and the first reset signal is input to the reset signal input terminals R of the slave microcomputers 4 and 5.
[0066]
Therefore, the first reset signal synchronized with the reset signal input terminals R of the slave microcomputers 4 and 5 can be input from the emulator 3.
[0067]
Thus, in the first embodiment, the capacitive load can be reduced by providing the slave microcomputers 4 and 5 that substitute for the function of the target microcomputer in the target probe 3b, and high-speed operation emulation can be realized.
[0068]
In addition, the clock oscillation circuit 16 provided in the target probe 3b can supply the second clock signal output from the clock oscillator 16a with a simple circuit configuration while sharing the second clock signal with the slave microcomputers 4 and 5, so that the application system 1 can be used. Debugging of a program can be easily performed without connection.
[0069]
Further, the reset signal input to the slave microcomputers 4 and 5 can be output as the first reset signal from the emulator 3 with a simple circuit configuration by the reset circuit 17 provided in the target probe 3b. Emulation at the time of reset start can be performed.
[0070]
(Example 2)
FIG. 4 is a main block diagram of an emulator provided with a trace function and a coverage function according to the second embodiment of the present invention.
[0071]
In the second embodiment, a trace circuit (trace means) 6a for sampling and tracing various data and status signals provided in the control circuit 6 and, for example, an execution address of the slave microcomputers 4 and 5 are displayed. A data acquisition signal circuit (data acquisition signal means) 18 for outputting a data acquisition signal capable of acquiring data at the same time as the coverage circuit (coverage means) 6b is provided.
[0072]
The trace circuit 6a is connected to the data bus 8 and the address bus 9, and predetermined data is obtained via the data bus buffer 12 and the address bus buffer 13. The coverage circuit 6b is connected to the address bus 9. , Predetermined data is obtained via the address bus buffer 13.
[0073]
The data acquisition signal circuit 18 includes an OR circuit 18a, which is an OR circuit, and inverters Iv8 to Iv10 for inverting a signal.
[0074]
The input sections of the inverters Iv8 and Iv9 of the data acquisition signal circuit 18 are connected to trace signal output sections for acquiring trace acquisition signals of the slave microcomputers 4 and 5, respectively.
[0075]
The outputs of the inverters Iv8 and IV9 are connected to the input of the OR circuit 18a, and the output is connected to the input of the inverter Iv10. The output of the inverter Iv10 is connected to the data of the trace circuit 6a and the coverage circuit 6b. It is connected to the acquisition signal input unit.
[0076]
Therefore, the trace acquisition signal of the Hi signal output from the trace signal output units of the slave microcomputers 4 and 5 is inverted by the inverters Iv8 and IV9 to be a Lo signal, and the output of the OR circuit 18a is also a Lo signal. The signal is inverted by an inverter Iv10 provided as a signal and becomes a Hi signal of a data acquisition signal, which is input to the data acquisition signal input sections of the trace circuit 6a and the coverage circuit 6b to acquire predetermined data.
[0077]
Accordingly, in the second embodiment, since the data acquisition signal is input to the trace circuit 6a and the coverage circuit 6b at the same time, the data acquisition of the trace data and the coverage data can be performed in a simultaneous sequence, thereby improving the debugging efficiency. Can be.
[0078]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Not even.
[0079]
For example, in the first and second embodiments, the clock oscillation circuit 16 and the reset circuit 17 and the data acquisition signal circuit 18 are provided separately, but the clock oscillation circuit 16, the reset circuit 17 and the data acquisition signal circuit 18 are all provided. It may be provided on a target probe (not shown).
[0080]
This allows more efficient emulation of a multi-CPU application system (not shown).
[0081]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0082]
(1) According to the present invention, the user interface and transmission lines can be reduced and the capacitive load can be reduced by providing slave microcomputers in one emulator by the number corresponding to the plurality of microcomputers provided in the application system. Since it can be reduced, emulation of high-speed operation can be realized.
[0083]
(2) In the present invention, a clock signal synchronized with a plurality of slave microcomputers can be supplied by the clock selection supply means provided in the emulator main body, so that program debugging can be performed without connecting an application system. It becomes possible.
[0084]
(3) Further, in the present invention, emulation at the time of reset start can be enabled by a clock selection supply unit that supplies a clock signal to a plurality of slave microcomputers provided in the emulator body.
[0085]
(4) Further, according to the present invention, by providing the data acquisition signal means, data acquisition of trace data and coverage data can be performed simultaneously.
[0086]
(5) Further, according to the present invention, according to the above (1) to (4), the efficiency of debugging in a multi-CPU application system provided with a plurality of microcomputers can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a connection diagram between an emulator and an application system according to a first embodiment of the present invention.
FIG. 2 is a main block diagram of the emulator according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram of a clock oscillation circuit and a reset circuit in the emulator according to the first embodiment of the present invention.
FIG. 4 is a main block diagram of a trace function and a coverage function in an emulator according to a second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Application system 2 Personal computer 3 Emulator 3a Emulator unit 3b Target probe 4 Slave microcomputer 5 Slave microcomputer 6 Control circuit 6a Trace circuit (trace means)
6b Coverage circuit (coverage means)
7 User Interface 8 Data Bus 9 Address Bus 10 Control Signal Bus 11 Control Signal Bus 12 Data Bus Buffer 13 Address Bus Buffer 14 Control Signal Bus Buffer 15 Control Signal Bus Buffer 16 Clock Oscillator (Clock Selection Supply Means)
16a Oscillator 16b AND circuit 16c AND circuit 16d to 16f OR circuit 17 Reset circuit (reset signal output means)
18. Data acquisition signal circuit (data acquisition signal means)
18a OR circuit Iv1 to Iv10 Inverter CA1 to CA3 Cable Ck Clock input terminal R Reset signal input terminal

Claims (4)

An emulator for debugging a multi-CPU application system provided with a plurality of microcomputers,
The emulator includes a plurality of slave microcomputers for performing functions of the microcomputer corresponding to the plurality of microcomputers provided in the application system, a user interface connected to the application system, and the plurality of slave microcomputers . An address bus and a data bus provided in common to the slave microcomputers; and a plurality of control buses individually provided in each of the plurality of slave microcomputers. The user interface includes the address bus and the data bus. And an emulator connected to a plurality of control buses . 2. The emulator according to claim 1, wherein, based on a first control signal, one of a first clock signal output from the application system and a second clock signal output from the emulator is selected. An emulator comprising clock selection supply means for supplying to a plurality of slave microcomputers. 3. The emulator according to claim 1, wherein a second control signal and a second reset signal output from the application system are input, and a reset signal for generating a signal for resetting the plurality of slave microcomputers. Output means, wherein the reset signal output means outputs a signal for resetting the plurality of slave microcomputers when the second control signal or the second reset signal is activated. An emulator that features. 4. The emulator according to claim 1, wherein the trace data and the coverage are input by inputting a data acquisition signal synchronized with a tracing means for sampling and tracing various data and status signals and a coverage means for displaying an execution address. An emulator comprising data acquisition signal means for acquiring data in a simultaneous sequence.

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