JPH05282179A - Emulator - Google Patents

Abstract

PURPOSE:To compact an emulator by controlling the reading operation of a brake condition and the writing operation of coverage information so as to time-dividedly execute them to/from a single memory. CONSTITUTION:In the case of executing brake condition setting and coverage relating to the execution address (PC address) of a processor in the first half of a clock cycle, a control part 3 allows an address switching part 2 to select a PC address 8 in accordance with a mode selection signal 16 and supplies the selected address 8 to a memory 1. Simultaneously with the assertion of an access strobe signal 12, the memory 1 is read out in order to acquire brake condition information. Data read out from the memory 1 are stored in a data register 7, and simultaneously a brake specifying part 5 judges whether both the brake conditions coincide with each other or not based upon the brake condition information. At the coincidence of both the brake conditions, a brake request signal 22 is asserted to a low level. In the latter half of the clock cycle, the coverage information is written in the memory 4 in accordance with the gate of the signal 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for debugging a user program to be debugged, and a technique for reducing the size of an emulator having a real-time trace function and a coverage trace function. Related to effective technology.

[0002]

2. Description of the Related Art In developing a microcomputer application device, an in-circuit emulator is used to debug the application system and perform a detailed evaluation of the system. The in-circuit emulator is connected between a system development device such as a parent computer (host computer) for software development and an application device under development, and functions of a microprocessor (target microprocessor) included in the application device. While acting as a substitute, it has a function as a debugger and supports detailed system debugging.

Some of such in-circuit emulators are provided with a coverage trace function in addition to a real-time trace function as means for enabling evaluation of a user program (target program) on the application device side. This coverage trace function makes it possible to grasp the execution address by storing the execution address of the target microprocessor in the memory and determining the contents of the memory at the end of emulation.

In this case, the execution address is stored in a predetermined memory (referred to as a coverage trace memory) arranged in an address space managed by the target microprocessor when the instruction is executed by the processor. It is enabled by setting the flag bit corresponding to the execution address. By the information thus sequentially stored in the coverage trace memory, it is possible to measure what percentage of the instruction word in the target program could be tested.

Incidentally, as an example of the document describing the in-circuit emulator, "Hitachi Microcomputer Technical Report (Vol. 2, No. 2)" issued by Hitachi Microcomputer Engineering Co., Ltd. on October 1, 1988. "
Also, there is "H8 / 520 ASE model-1 User's Manual" issued by Hitachi, Ltd. in March, 1990.

[0006]

By making the coverage memory and the break memory common, the emulator can be downsized, but in the emulation operation, the write operation is performed in the coverage memory and the read operation is performed in the break memory. However, according to the conventional technique, such operations compete with each other in the same cycle, which makes it difficult to standardize the memories. That is, since the coverage memory circuit and the break memory circuit have many parts having the same function including the peripheral parts thereof, they must be realized by independent circuit blocks in terms of hardware. Inevitably the circuit scale increases,
This has hindered the miniaturization of emulators.

An object of the present invention is to provide a technique for reducing the size of an emulator by sharing a coverage memory and a break memory.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, the coverage information storing means for enabling the writing of the coverage information regarding the execution of the user program by the microprocessor, and the emulation operation when the control state of the microprocessor and the state of the slave bus reach a preset state. When the emulator is configured to include break condition storage means capable of storing break conditions for stopping, the break conditions are read and the coverage information is written in a single memory in a time-division manner. Is provided.

[0011]

According to the above-mentioned means, the control means controls the reading of the break condition and the writing of the coverage information so as to be performed on a single memory in a time-division manner. The memory means and the break condition memory means can be realized by a single memory, and the emulator can be miniaturized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows the structure of the main part of an in-circuit emulator which is an embodiment of the present invention.

Although not shown, the in-circuit emulator 50 shown in the figure is connected between a parent computer and a microprocessor application device under development, and substitutes the function of a target microprocessor included in the application device. On the other hand, it has a function as a debugger and supports detailed system debugging. Although not particularly limited, the parent computer and the in-circuit emulator 50 are connected by a serial line bus line or the like, and this bus line enables data exchange between the two. In addition, the cable 4 from the in-circuit emulator 50
0 is pulled out, and the plug 41 provided at the tip of the cable 40 is connected to the socket for the target microprocessor of the applied device, so that the in-circuit emulator 50 can perform a predetermined emulation operation.

As shown in FIG. 3, the in-circuit emulator 50 is not particularly limited, but in place of the function of the target microprocessor included in the microprocessor application device, the operation control or emulation of the application device is performed. A slave microprocessor (hereinafter, referred to as SMCU) 38 and a master microprocessor (hereinafter, referred to as MMCU) 31 that controls the control for achieving various debug functions are mounted.

When the SMCU 38 controls (emulates) the function of the target microprocessor in the application device, the SMCU 38 is disconnected from the control of the MMCU 31, and the control operation state of the SMCU 38 reaches a predetermined state and breaks. When MM
It will be controlled by the CU 31. The switching of the control state is performed by the emulation control unit 33.

In addition to the emulation controller 33, the in-circuit emulator 50 monitors the control state of the SMCU 38 and the state of the slave bus 37 and stops the emulation operation when the state reaches a preset state. Break control function and a coverage control function that performs a coverage trace according to a passage address of a program executed by the SMCU 38, and a data and address given to the slave trace 37 and a coverage trace unit 36, and a slave bus 37. A real-time trace unit 34 that sequentially traces and stores information,
It has a proxy memory unit 35 for acting as a data memory or a program memory to be included in the application device, which are connected to the SMCU 38 via the slave bus 37 and to the MMCU 31 via the master bus 32.
The function execution of each block can be controlled from the console of the parent computer connected to the in-circuit emulator 50.

Further, a cable 40 is pulled out from the SMCU 38 through the interface circuit 38, and a plug portion 41 provided at the tip of the cable 40 is connected to a socket for a target microprocessor of a microprocessor application device. It is like this.

FIG. 1 shows an example of the configuration of the coverage trace unit 50, and FIG. 2 shows the operation timing of the main part of this embodiment.

The PC address generator 27 generates a PC (program counter) address based on the address transmitted by the address bus 9 included in the slave bus 37 and the MPU status. An address switching unit 2 for selecting an address transmitted by the address bus 9 and a PC address fetched from the PC address generating unit 27 is arranged at the subsequent stage of the PC address generating unit 27, and is selected by the address switching unit 2. Address is transmitted to the address terminal (Address) of the memory 1 in the subsequent stage. The input / output terminal DIO of the memory 1 is coupled to the input terminal of the data register 7, the input terminal of the break determination circuit 5, and the output terminal of the data processing unit 6, and data can be exchanged with them. .. The output terminal of the data register 7 is coupled to the first input terminal IN1 of the data processing unit 6 in the subsequent stage via the data register bus 18. The data bus 15 is coupled to the second input terminal IN2 of the data processing unit 6, and the data input via the data bus 15 is taken into the data processing unit 6. The data processing unit 6 performs data processing such as a predetermined logical operation on the input data and outputs it to the memory data bus 17.

The break determination circuit 5 monitors the state of the memory data bus 17 and determines whether or not a preset break condition is satisfied. When the preset break condition is satisfied, the break request signal 22 * (* indicates low active or signal inversion) is asserted to the low level. Data on the memory data bus 17 can be transmitted to the data bus 15 via the data output buffer 4.

The control unit 3 controls the break control and the operation control of the entire coverage trace unit 36. The control unit 3 outputs the address switching signal 20 to the address switching unit 2 and the memory 1 to the memory 1. The control signal 19 is output, the memory control signal 26 is output to the data register 7, the data processing control signal 23 is output to the data processing unit 6, and the break determination signal is output to the break determination circuit 5. 25 is output. The control unit 3 includes a basic clock Φ, a read / write signal R / W *, a coverage memory decode signal CVR *, and a break memory decode signal BM.
*, Access strobe signal 12, mode selection signal 16
Is input, and an operation control signal for each block of the break control and coverage trace unit 36 is generated based on each of these signals.

FIG. 2 shows the operation timing of the main part of the break control and coverage trace section 36.

Although not particularly limited, in the emulator of this embodiment, one access cycle consists of two basic clock cycles.

First, the access A during the emulation operation will be described.

In the first half clock cycle (T1), when setting the break condition and covering the execution address of the processor (hereinafter referred to as the PC address), the control unit 3 causes the address switching unit 2 to send the PC address Is selected and is supplied to the memory 1. Further, the address bus 9 is selected when setting break conditions and covering the access address. Then, at the same time when the access strobe signal 12 * is asserted, the memory 1 is read to obtain the break condition information.

The data read from the memory 1 is stored in the data register 7, and at the same time, the break determination unit 5 determines whether the break conditions match based on the break condition information. If they match, the break request signal 2
Assert 2 * low. In the latter half clock cycle (T2), the coverage information is written in the memory 1 in accordance with the negation of the access strobe signal 12.

That is, the first half clock cycle (T1)
Then, a PC break (read operation of memory 1) is performed,
A coverage trace (write operation of the memory 1) is performed in the latter half clock cycle (T2), and by accessing the memory 1 in such a time division manner, a break condition storage unit for storing the break condition, and a coverage condition. The coverage information storage unit that enables writing of information can be realized by the single memory 1.

When writing the coverage information,
In the data processing unit 6, from the data in the data register 7 and the write data of the coverage information, the mode selection signal 16
In accordance therewith, data processing such as a logical operation selected via the control unit 3 is performed, and data to be written in the memory 1 is created. By such data processing, it becomes possible to write or change the coverage information and hold or change the break condition information at the same time. For example, it is possible to perform conditional coverage or breaks with a specified number of times. Further, since the target of access from the SMCU 38 during this period is not the coverage memory or the break memory (both are realized by the memory 1), the read / write signal R /
The state of W *, the decode signal CVR *, the break memory decode signal BM *, and the data bus 15 to / from which data relating to the access target is input / output are not related to the operation of the circuit 50.

Next, the access B other than during the emulation operation will be described.

In the read operation, when the read / write signal R / W * is read as in a normal memory, the decode signal CVR *, the break memory decode signal BM *,
Address bus 9 according to access strobe signal 12 *
The data designated by the address transmitted by is transmitted to data bus 15 via data output buffer 4. The writing is as follows.

In the first half clock cycle (T3), the emulation operation is performed in the same manner as described above except that it is not necessary to determine whether the break conditions match and that the PC address is not selected. In the latter half of the clock cycle (T4), the data processing unit 6 receives the decode signal CVR * from the data in the data register 7 and the write data obtained from the SMCU via the data bus 15.
Alternatively, data in which only the coverage information or break condition information selected by BM * is rewritten is created and written in the memory 1. This allows the coverage information and the break condition information to be held or changed independently.

At this time, in the data processing unit 6,
From the data of the data register 7 obtained via the register data bus 18 and the write data obtained from the SMCU via the data bus 15, data such as logical operation selected via the control unit 3 according to the mode selection signal 16 is stored. It is also possible to process and create data to be written in the memory 1. By such data processing, it becomes possible to hold or change the coverage information and the break condition information at the same time and in a mutually related form. For example, it is possible to easily make a break setting based on the current coverage information.

According to the above embodiment, the following operational effects can be obtained.

(1) First half clock cycle (T1)
Then, a PC break (read operation of memory 1) is performed,
A coverage trace (write operation of the memory 1) is performed in the latter half clock cycle (T2), and by accessing the memory 1 in such a time division manner, a break condition storage unit for storing the break condition, and a coverage condition. The coverage information storage means capable of writing information can be realized by the single memory 1, and the peripheral portion of the memory can be shared by this, and the emulator can be miniaturized.

(2) At the time of writing the coverage information, in the data processing unit 6, the logical operation selected from the data of the data register 7 and the write data of the coverage information according to the mode selection signal 16 via the control unit 3. Data processing such as is performed, data to be written in the memory 1 is created, and by such data processing, it is possible to write or change coverage information and hold or change break condition information at the same time. , Break setting and coverage information can be related to each other, and a composite function can be realized.

Although the invention made by the present inventor has been described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, system and emulation 2
The data processing unit 6 may be connected to a system bus, or the data processing process by the data processing unit 6 may be omitted.

In the above description, the invention made by the present inventor was mainly described as an in-circuit emulator which is a field of application which is the background of the invention. However, the present invention is not limited thereto, and a system of microcomputer application equipment is used. It can be applied to various emulators that enable debugging.

The present invention can be applied on condition that it includes at least a real-time trace function and a coverage function.

[0040]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the read operation of the break condition and the write operation of the coverage information are controlled to be performed in a time-division manner with respect to a single memory, so that the coverage storage means and the break condition storage means are unified. It can be realized by the memory of, and the emulator can be miniaturized.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a main part of an in-circuit emulator according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of a main part of the in-circuit emulator.

FIG. 3 is an overall configuration block diagram of the in-circuit emulator.

[Explanation of symbols]

 1 memory 2 address switching unit 3 control unit 4 data output buffer 5 break request signal 6 data processing unit 7 data register 27 PC address generation unit 31 MMCU 32 master bus 33 emulation control unit 34 real-time trace unit 35 proxy memory unit 36 break control and coverage Trace part 37 Slave bus 38 SMCU 39 Interface 40 Cable 41 Plug 50 In-circuit emulator

Claims (2)

[Claims] 1. Coverage information storage means for enabling the writing of coverage information for execution of a user program by a microprocessor, and emulation operation when the control state of the microprocessor or the state of the slave bus reaches a preset state. An emulator including break condition storage means capable of storing break conditions for stopping includes a control means for performing time-division of break condition reading and coverage information writing on a single memory. An emulator characterized in that the coverage storage means and the break condition storage means are realized by a single memory. 2. The emulator according to claim 1, wherein the control means allocates a first half of one cycle in emulation execution to a read operation of a break condition and a second half of the one cycle to a write operation of coverage information.