JPH04314139A - Debugging device - Google Patents

Abstract

PURPOSE:To realize the partial change of the flow of a program or processing contents irrespective of the presence of a free area of a user program and besides, without correcting directly an original program. CONSTITUTION:By providing a patch memory 42 to which a patch program related to the correction of the user program can be written and a trigger detection circuit 39 to detect that the execution of the user program reaches a prescribed patch designating place, and further, providing a bus control part 40 or multiplexers 34 to 37 as a means to enable the execution of the patch program by switching space from a lent memory 43 to the patch memory 42 based on the output of this detection circuit 39, the patch program is made capable of being written in the patch memory 42 under the executing state of the user program, and when the execution of the user program reaches the prescribed patch designating place, the patch program in a second memory is executed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugging device that enables debugging of a program to be debugged, and relates to a technique that is effective when applied to, for example, an in-circuit emulator.

0002

2. Description of the Related Art In the development of microprocessor application equipment, in-circuit emulators are used to debug the application system and perform detailed evaluation of the system. Such an in-circuit emulator is connected between a system development device such as a software development parent computer (host computer) and an application device under development, and is used to control the microprocessor (target microprocessor) included in the application device. While acting as a debugger, it supports detailed system debugging. Such an in-circuit emulator has a user program editing function in addition to a break function and a trace function as a means for evaluating the hardware and software on the application equipment side.

[0003] An example of a document describing in-circuit emulators is "Hitachi Microcomputer Technical Report (Vol. 2, No. 2)," published by Hitachi Microprocessor Engineering Co., Ltd. on October 1, 1985. )”
There is.

0004

[Problem to be Solved by the Invention] When applying a patch in system debugging that makes full use of the above functions, it is necessary to modify the program. A general method for modifying a program is to temporarily stop the user program, find an empty area in the user program area, write the modified program there, and change the flow of the program to the modified program side. It is necessary to rewrite some instructions to jump instructions, jump subroutine instructions, etc., and the inventor studied this and found that if the program is modified by creating a wait state while the emulation operation is being executed, the motor rotation In application equipment that requires the execution of a program under strict time management, such as control equipment, if the execution of the program is interrupted in such a waiting state, equipment such as servo motors that should be controlled by the program It was discovered that there is a possibility that the robot could escape from its control state and go out of control. Furthermore, it has been revealed that when there is little free space for storing a modification program, the above modification method becomes impossible, and the original program must be directly modified and recompiled, resulting in a decrease in debugging efficiency.

[0005] An object of the present invention is to provide a technology that makes it possible to partially change the program flow and processing contents, regardless of whether or not there is a free area in the user program, and without directly modifying the original program. In particular, another object of the present invention is to provide a technique that allows such patch programs to be inserted and executed in real time.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, when a debug device is formed including a first memory for storing a user program to be debugged, a patch program for modifying the user program is written while the user program is being executed. a detecting means for detecting that the execution of the user program has reached a predetermined patch specified location; and a space from the first memory to the second memory based on the detection result of the detecting means. A debugging device is configured including a space switching means that enables execution of the patch program in the second memory by switching. In a more specific aspect, a multiplexer for selectively coupling the first memory and the second memory to the bus of the master microprocessor and the bus of the slave microprocessor; The space switching means may include a control section that controls the selection operation. At this time, while the first memory is coupled to the bus of the slave microprocessor via the multiplexer and the emulation operation of the user program continues, the second memory is coupled to the bus of the master microprocessor. By coupling, a logic circuit that enables writing of the patch program to the second memory can be included in the control section.

[0009]

[Operation] According to the above means, it is possible to write a patch program into the second memory while the user program is being executed, and when the execution of the user program reaches a predetermined patch specification location, the patch program can be written into the second memory while the user program is being executed. 2, the execution of the patch program in the memory is shifted to the execution of the patch program in the memory.
To make it possible to partially change the program flow and processing contents without directly modifying the original program, and also to enable real-time insertion and execution of the patch program.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows a microprocessor development system including an in-circuit emulator, which is an embodiment of the present invention.

The in-circuit emulator body 2 shown in FIG. 2 includes a system development device 1 such as a parent computer, and a microprocessor application device 3 as a device to be debugged.
The microprocessor 3 is connected between the application device 3 and performs the functions of the target microprocessor included in the application device 3, while also functioning as a debugger and supporting detailed system debugging. The system development device 1 and the in-circuit emulator main body 2 are connected by a serial bus line, and this bus line allows data to be exchanged between the two. In addition, the interface cable 4 is pulled out from the in-circuit emulator main body 2,
A plug 4a provided at the tip of this cable 4 is coupled to a target microprocessor socket 5 of the application device 3, thereby enabling a predetermined emulation operation in the main body of the in-circuit emulator 2.

FIG. 2 shows a detailed configuration of the in-circuit emulator 2. As shown in FIG.

As shown in FIG. 2, the in-circuit emulator body 2 includes a microprocessor application device 3.
A slave microprocessor (hereinafter referred to as SM
CU) 11, and a master microprocessor (hereinafter referred to as MMC) that controls control for achieving various debugging functions.
(denoted as U) 16 is provided.

When the SMCU 11 performs proxy control (emulation) of the functions of the target microprocessor in the application device 3, the SMCU 11
When the control operation state of the SMCU 11 reaches a predetermined state and is broken, the SMCU 11 is controlled by the MMCU 16. Such switching of control states is performed by the emulation control section 12.

In addition to the emulation control section 12, the in-circuit emulator body 2 includes an SMCU 1.
1 and the state of the slave bus 21 and stop the emulation operation when the state reaches a preset state, the data and address given to the slave bus 21, and It has a real-time trace section 14 that sequentially traces and stores control information, and a substitute memory section 15 that substitutes data memory and programs to be included in the application device 3. It is connected to the MMCU 16 via the master bus 22. The function execution of each block above is performed in-circuit.
It is controlled by a console 10 of a parent computer connected to the emulator main body 2.

Furthermore, a serial interface circuit 17 is provided in the in-circuit emulator body 2 for data communication between the MMCU 16 and the console 10, and the cable is connected from the SMCU 11 via the interface circuit 18. 4 is drawn out.

FIG. 1 shows a detailed configuration of the main parts of the in-circuit emulator main body 2 shown in FIG. 3. As shown in FIG.

As shown in FIG. 1, the slave bus 21
are slave address bus 30, slave data bus 31
The master bus 22 includes a master address bus 32 and a master data bus 33. The proxy memory unit 15 in FIG. 2 includes, but is not particularly limited to, a rental memory for storing a user program to be debugged (
In addition to the first memory) 42, a patch memory (second memory) 43 is included in which a patch program for modifying the user program can be written while the user program is being executed. Although not particularly limited,
Multiplexer (MPX) for data transmission path switching
34, 35, 36, 37, an address counter 38 of the patch memory 42, a trigger detection circuit 39 as a detection means for detecting that the execution of the user program has reached a predetermined patch designated location, a rental memory 43 and a patch memory 42; A bus control unit 40 for space switching, and an interrupt control unit 4 for controlling interrupts from the bus control unit 40.
1 etc. are arranged.

The bus control section 40 asserts an interrupt request signal RQ to a low level to the interrupt control section 41 according to the instruction of the detection signal TRG from the trigger detection circuit 39. The interrupt control unit 41 that received the instruction is the SMC
An interrupt signal IRQ is issued to U11. Also,
The bus control unit 40 has a function of generating select signals M1 and M2 for selecting the rental memory 43 and the patch memory 42. Although not particularly limited, when performing data setting such as during initialization, the select signal S is asserted to a low level, and the multiplexer 34,
35, 36, and 37 are each switched to the B terminal side. Further, when the select signal S is asserted to a high level, the multiplexers 34, 35, 36, and 37 are respectively switched to the A terminal side. Each of the above control signals RQ
, S signals are synchronized with the clock signal CLK of the SMCU 11. Further, the counter clock CK of the address counter 38 for the patch memory 42 is CL.
Generated based on K. The initial value of the counter 38 can be set from the MMCU 16 via the data bus 33, so that counting can be started from any value at the timing of the CLK signal.

FIG. 4 shows a detailed configuration example of the bus control section 40.

51 is a D latch circuit, and this D latch circuit 51 synchronizes with the output TRG of the trigger detection circuit 39 and the D
The AND with the Q* output (* indicates low active or data inversion) of the latch circuit 51 is latched. This D
The Q output of the latch circuit 51 is transmitted to the interrupt control section 41 in FIG. 1 as a request signal RQ. 52 is a counter, and this counter 52 counts the Q* output of the D latch circuit 51 in synchronization with the clock CL. The logical product of the output of the counter 52 and the control signal E1* is used as a timing signal for connecting the patch memory 42 to the slave side, and is preset in the latch circuit 53 at the subsequent stage. The control signal E1* is an instruction signal for switching the rental memory 43 to the master space, and is asserted by the emulation control unit 12 when initializing the rental memory 43 or loading a user program. The comparator 5 determines whether a return command indicating the end of the patch program has appeared on the slave data bus 31.
4, and the latch circuit 53 is cleared by ANDing the output of the comparator 54 and the control signal E2*. The control signal E2* is an instruction signal for switching the patch memory 42 to the master space, and is asserted by the emulation control unit 12 when writing a patch program to the patch memory 42. The output of the latch circuit 53 is the multiplexer 3 shown in FIG.
This is the select signal S for selection operations 4 to 37. This select signal S is also transmitted to multiplexers 55 and 56 in the bus control section 40 as their selection control signals. 57 is a decoder that decodes, for example, the upper few bits of the master address bus 32, and the decoded output of this decoder 57 is sent to the A terminal of the multiplexer 55;
The signal is transmitted to the B terminal of multiplexer 56. Furthermore, the B terminal of the multiplexer 55 and the A terminal of the multiplexer 56 are connected to a control signal E3* indicating that the user program is being executed.
is inputted from the emulation control unit 12, and the multiplexers 55 and 56 can select the control signal E3* or the output of the decoder 57 depending on the output state of the latch circuit 53. multiplexer 5
The selection output M1 of the multiplexer 56 is transmitted to the rental memory 43, and the selection output of the multiplexer 56 is transmitted to the patch memory 42. Furthermore, the control signal E3* and the multiplexer 56
The logical OR with the output of is transmitted to the address counter 38 for the patch memory 42 as an on signal CON for operating the address counter 38.

Next, the emulation operation of the above configuration will be explained.

When starting the emulation operation, by asserting the select signal S to high level and the control signal M1 to low level, the rental memory 43 is connected to the master bus 22 of the MMCU 16, and the initial setting of the rental memory 43 is performed. It is possible to download a user program or input a program by the user. At this time, the control signal M1 enables the rental memory 43 and also enables the buses 46 and 47 of the multiplexer 36. With the above initial settings, the program to be debugged by the user is placed on the rental memory 43. Next, according to an instruction from the emulation control section 12, the select signal S and the M1 signal output from the bus control section 40 are set to low level. As a result, SMCU1
The rental memory 43 is connected to the slave bus 21 of No. 1, and the execution of the user program to be debugged is started.

Next, when the control signal M2 is asserted to a low level, the patch memory 42 is connected to the master bus 22 of the MMCU 16, and the patch memory 42 is enabled to write the modified portion of the user program. The user inputs a program correction part into the patch memory 42 as necessary, and sets an address or condition for replacing the rental memory 43 from the MMCU 16 to the trigger detection circuit 39. At this stage, the MMCU 16 initializes the counter 38 (setting the starting address of the patch memory 42). Above M
Patch memory 42 and trigger detection circuit 3 by MCU 16
9 and the setting of the counter 38, the SMCU 11 continues to emulate the user program in the rental memory 43. When the above settings are completed, the trigger detection circuit 39 successively compares the trigger condition settings with the slave bus 21 of the SMCU 11. In the comparison, if it is detected that the conditions match, that is, that the program to be debugged has reached the specified patch location, the trigger detection circuit 39 asserts the detection signal TRG.

In the bus control unit 40, when the detection signal TRG is asserted, an interrupt request signal RQ is issued in synchronization with the clock signal CLK, the select signal S is set to high level after stacking, and the control signal M2 is set to low level. level. As a result, data bus 31 of SMCU 11
and the counter 38 are connected to the data bus 44 of the patch memory 42,
Connected to address bus 45. Counter clock CK synchronized with clock signal CLK of SMCU11 after connection
The counting operation of the counter 38 is started, and the contents of the patch memory 42 (program related to correction) are sequentially sent to the SMCU 11 using this counted output value as an address, and the patch program is executed by the SMCU 11. Termination of the patch program is made possible by detecting a return instruction written in the last part of the patch program. That is, the above return command causes the comparator 54 in the bus control unit 40 to clear the latch circuit 53, thereby setting the select signal S to a low level, thereby returning the program area to the lending memory 43. With the above operations, the insertion of the patch program is completed without stopping the user program to be debugged.

According to the above embodiment, the following effects can be obtained.

(1) A patch memory 42 into which a patch program for modifying the user program can be written while the user program is being executed, and a trigger that detects that the execution of the user program has reached a predetermined patch specified location. The detection circuit 39 and the bus control unit 40 and the multiplexer 34 are used as means for enabling the execution of the patch program by switching the space from the rental memory 43 to the patch memory 42 based on the detection result of the detection circuit 39. 37, it is possible to write a patch program into the patch memory 42 while the user program is being executed, and when the execution of the user program reaches a predetermined patch designated location,
By shifting to the execution of the patch program in the second memory, part of the program flow and processing contents can be changed regardless of whether there is free space in the user program or without directly modifying the original user program. Furthermore, it is possible to insert and execute the patch program in real time.

(2) Rental memory side multiplexers 36 and 37 for selectively coupling the rental memory 43 to the MMCU 16 and SMCU 11;
6 and the patch memory side multiplexer 34 for selectively coupling the patch memory 42 to the SMCU 11;
35 and a control unit that controls the selection operations of these multiplexers, the function of the space switching means described above can be easily realized.

(3) While the rental memory 43 is connected to the bus 21 of the SMCU 11 via the multiplexers 36 and 37 and the emulation operation of the user program is continued, the patch memory 42 is transferred to the MMCU 16.
By coupling the bus 22 to the bus 22, the function of writing the patch program into the patch memory 42 can be appropriately realized by the logic circuit within the bus control unit 40.

(4) Emulation efficiency can be improved by the effect of (1) above.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and can be modified in various ways without departing from the gist of the present invention.

For example, in the above embodiment, the patch memory 4
2 and counter 38, but by providing a plurality of counters 38 and further providing means for selecting them, it may be possible to register a plurality of patch programs on one patch memory 42 by changing the address, Alternatively, a plurality of patch memories 42 may be provided. Further, the data bus of the patch memory 42 may be expanded and the end point of the patch program may be recorded in an empty bit to supplement the control of the bus control unit 40.

Furthermore, in the above embodiment, the patch memory 42
Although we have explained that an interrupt is issued to the SMCU 11 when switching to the may be changed. In addition, it is possible to reduce the circuit scale by breaking the trigger detection circuit or reusing the trace trigger circuit, and by providing an on/off function for the registered trigger conditions, the usability of the emulator can be improved.

In the above description, the invention made by the present inventor was mainly applied to an in-circuit emulator, which is the background field of application, but the present invention is not limited thereto, and is applicable to a tester. It can be applied to other debugging devices having emulation functions such as the following.

The present invention can be applied to conditions that are coupled to or include at least a processor that executes a program to be debugged.

[0036]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to write the patch program into the second memory while the user program is being executed, and when the execution of the user program reaches a predetermined patch specification location, the patch program in the second memory is written. By moving to execution, it is possible to partially change the program flow and processing contents regardless of whether or not there is free space in the user program, and without directly modifying the original program. It is possible to insert and execute programs in real time.

[Brief explanation of the drawing]

FIG. 1 is a detailed configuration block diagram of the main parts of an in-circuit emulator according to an embodiment of the present invention.

FIG. 2 is an overall configuration block diagram of an in-circuit emulator according to an embodiment of the present invention.

FIG. 3 is a block diagram of a microprocessor development system including the in-circuit emulator.

FIG. 4 is a logic circuit diagram of the bus control section shown in FIG. 1;

[Explanation of symbols]

2 In-circuit emulator body 11 Slave microprocessor 12 Emulation control unit 13 Break control unit 14 Trace memory 15 Alternative memory 16 Master microprocessor 17 Serial interface 18 Interface 21 Slave bus 22 Master buses 34 to 37 Multiplexer 38 Counter 39 Trigger detection circuit 40 Bus Control unit 41 Interrupt control unit 42 Patch memory 43 Rental memory

Claims (3)

[Claims] 1. A debugging device including a first memory for storing a user program to be debugged and capable of debugging the user program, comprising:
While the above user program is running, there is a second
a memory, a detection means for detecting that the execution of the user program has reached a predetermined patch designated location, and a space switching from the first memory to the second memory based on the detection result of the detection means. and space switching means that enables execution of the patch program in the second memory. 2. When the space switching means includes a master microprocessor for achieving various debugging functions and a slave microprocessor for performing emulation, the space switching means is configured to switch between a bus of the master microprocessor and a bus of the slave microprocessor. Toni above 1st
2. The debugging device according to claim 1, comprising: a multiplexer for selectively coupling the memory and the second memory; and a control section for controlling selection operations of the master-side multiplexer and the slave-side multiplexer. 3. The control unit controls the second memory to be connected to the second memory while the first memory is coupled to the bus of the slave microprocessor through the multiplexer and the emulation operation of the user program is continued. 3. A debugging device according to claim 2, further comprising a logic circuit coupled to a bus of a master microprocessor to enable writing of said patch program into said second memory.