JPH04125740A - Microcomputer and emulator - Google Patents

Abstract

PURPOSE:To evaluate the application system of a large-scale semiconductor integrated circuit by providing an interface means which outputs discrimination information of a CPU module, which generates a bus cycle, to the external together with information for trace of the operation of each CPU module. CONSTITUTION:At the time of emulation of a target system 40, an evaluating microcomputer 1 outputs the discrimination codes of CPU modules 2,3, and 4 which generate the bus cycle or bus master modules 5 and 6 to an emulator 21 together with information appearing on internal busses 10 and 11. Consequent ly, the emulator 21 receives these discrimination codes to perform the break point control while recognizing classifications of CPU modules 2,3, and 4 and bus master modules 5 and 6. Further, correspondence between trace results and CPU modules 2,3, and 4 or bus master modules 5 and 6 is easily obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an evaluation microcomputer and an emulator used in emulation, and relates to an evaluation microcomputer and an emulator that are used for emulation. The present invention relates to a technique that is effective when applied to a microcomputer used to evaluate an application system of an on-chip large-scale semiconductor integrated circuit, and an emulator that uses the microcomputer.

[Prior Art] An emulator is a microcomputer to be installed in a target system (hereinafter also simply referred to as a target microcomputer) when performing software debugging or system debugging in the development of a microcomputer application device (hereinafter also simply referred to as a target system). ), it basically supports system debugging while acting on behalf of the target microcomputer's functions, and allows the emulator to monitor its control status and change its control status from the emulator side. A microcomputer for evaluation is required.

Since a conventional microcomputer is limited to one built-in CPU module, the emulator side interface in the evaluation microcomputer is limited to one built-in CPU module.
The information on the internal bus to which each CPU module is connected is output so that the operation of the CPU module can be monitored on the emulator side.

For example, when configuring a multiprocessor system using a conventional microcomputer with only one built-in CPU module, multiple microcomputers are used, and for such system evaluation, each microcomputer has an evaluation module. System debugging and software debugging can be performed by preparing a microcomputer and an emulator.

An example of a document describing a conventional evaluation microcomputer is the H81570 Evachip Specification published by Hitachi, Ltd. in April 1990.

[Problem to be solved by the invention]

Nowadays, semiconductor integrated circuits are becoming more and more highly integrated due to advances in process technology, and the trend toward system-on-chip systems, as typified by single-chip microcomputers, is accelerating.

The present inventor studied a technique for evaluating an applied system of a microcomputer when converting a conventional system composed of a plurality of microcomputer LSIs and peripheral circuit LSIs into a single chip microcomputer. As with conventional evaluation microcomputers, it is not possible to simply output information on all internal buses to which CPU modules are connected from the emulator interface side. It has been found that it is difficult to easily determine whether the output information relates to the operation of which CPU module, and there is a possibility that system evaluation cannot be performed efficiently. Moreover, on the emulator side, a new function is required to control and monitor the emulation operation for each CPU module built in the evaluation microcomputer.

An object of the present invention is to provide a microcomputer that can be used to evaluate an application system of a large-scale semiconductor integrated circuit that incorporates a plurality of CPU modules and is configured as a system-on-chip, and an emulator suitable for the microcomputer. It is in.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when a microcomputer used for emulation of the evaluation target system includes multiple CPU modules, the CPU that generated the bus cycle is recorded along with information for tracking the operation of each CPU module.
An interface means for outputting module identification information to the outside is provided. Identification information is CPU
It is possible to enable output not only for the module but also for other bus master modules.

In addition, the evaluation microcomputer is connected to multiple CPs.
Target interface means that incorporates the U module and enables connection of all or some of the internal buses to which the CPU module is coupled to the evaluation target system, and connects all of the internal buses to which the CPU module is coupled to the emulator system. When the emulator interface means has an information output function for tracking the operation of each CPU module, the emulator interface means has an information output function for tracking the operation of each CPU module, and a
This assigns the function of outputting the identification information of the PU module to the outside.

In addition, in order to configure an emulator for emulating a system to be evaluated using a microcomputer having such an input/output means in the emulator interface means, a trace means that sequentially stores input information in synchronization with bus cycles is required. It is preferable to provide each of the input/output means with a break means for detecting coincidence between input information and expected value information and generating a break signal.

[For production]

According to the above means, the evaluation microcomputer outputs the input/output information of the CPU module that generates the bus cycle in the emulation of the evaluation target system, as well as the identification information of the CPU module, to the emulator, and the emulator receives the input/output information of the CPU module. , operating CP
Breakpoint control and tracing are performed while making it possible to understand the type of U module. The evaluation microcomputer has a function to output this information for each internal bus to which the CPU modules are connected, so even if the CPU modules operate in parallel or share an internal bus, real-time performance is possible. It becomes possible to obtain the necessary information and evaluate the target system.

〔Example〕

FIG. 1 shows an evaluation microcomputer according to an embodiment of the present invention.

The microcomputer 1 shown in the figure is, although not particularly limited, a relatively large-scale system such as a multiprocessor system integrated into one chip, for example, three
Mainly CPU module 2゜3.4, other path master module 5.6, peripheral circuit module 7.8
, and DPRAM (dual port random access memory) 9, which are appropriately connected to two systems of internal buses 10 and 11, respectively.
An input/output port 12.13 as a target interface means and an emulator input/output circuit 14.15 as an emulator interface means are connected to the emulator.

The CPU module 3 has two internal buses 10 and 11.
The DPRAM 9 is used for exchanging information between the internal buses 10 and 11, and the internal bus 10 also has a path master module 5.
, a CPU module 2, and a peripheral circuit module 7, and a path master module 6, a CPU module 4, and a peripheral circuit module 8 are also connected to the other internal bus 11.

The CPU modules 2, 3.4 execute instructions according to a predetermined procedure according to an operation program stored in a program ROM included in the internal peripheral circuit module 7.8 or an external program ROM (not shown). The CPU modules 2, 3.4 do not have to be identical to each other, and may operate synchronously or asynchronously with each other.

The path master module 5.6 is set with necessary functions, such as a direct memory access controller and a coprocessor that starts a bus cycle.

The peripheral circuit module 7.8 includes a timer, a serial communication interface controller, an A/
Necessary circuits such as a D converter, D/A converter, and RAM are included.

The internal buses 10 and 11 serve as transmission paths for data, addresses, control signals, and the like.

The input/output ports 12.13 may be configured to specifically interface the addresses and data of the internal bus 10.11 with the outside, or may be used to interface specific circuits such as timers and serial communication interface controllers included in the peripheral circuit module 7.8. Functions for external input/output may be assigned, and the input/output functions are not limited.

The explanation up to this point except for the emulator input/output circuits 14 and 15 is basically the same as that of the target microcomputer as a real chip supported by the evaluation microcomputer of this embodiment, and the input/output ports 13 and 12 are This corresponds to the external input/output function originally provided by the computer, and in the case of an evaluation microcomputer, it is connected to the target microcomputer mounting area of the target system.

The emulator input/output circuit 14.15 has a function of outputting to the outside all of the information that appears on the internal bus 10.11 at least when the CPU modules 2 and 3.4 are activated in a bus cycle. Even if the signal line is not released, the internal bus 10
．． All 11 signal lines are opened to the outside and can be connected to an emulator (not shown). In fact, the emulator input/output circuits 14 and 15 acquire information for the emulator to monitor rebreak points traced to the internal operating state of the microcomputer 1, and control internal operating states or control states from the emulator side. It is used for inputting and outputting information.

The CPU modules 2, 3.4 and the bus master modules 5, 6 are each given a unique identification code,
When starting a bus cycle, the identification code is output to the corresponding ID bus 16.17 and output from the emulator input/output circuit 14.15 to the outside. I
The D buses 16 and 17 are divided into two systems corresponding to the internal buses 11 and 12. The identification code output function is easily achieved by opening a register in which an identification code is set in advance and outputting the same code in synchronization with the assertion timing of an address strobe signal that corresponds to the activation of a bus cycle. can do.

FIG. 2 shows an emulator 21 according to an embodiment of the present invention.

The emulator 21 shown in the figure has emulation buses 22.
23, trace circuits 24, 25, breakpoint control circuits 26, 27, emulation control circuit 28
．． 29 are individually coupled, and the proxy memory circuit 3
0 is connected. The identification code output from the microcomputer is connected to the trace circuit 24.25 and the breakpoint control circuit 26.27 via the ID bus 31.3.
2.

The trace circuits 24, 25, breakpoint control circuits 26, 27, etc. are also coupled to a control bus 33, and are configured to set various conditions for emulation, control the transfer of trace information, etc. under the control of a control processor 34. It has become. This control bus 33 is provided with a system interface circuit 35 connected to a system development device 38, and a work RA
A control program ROM 37 for the M36 and control processor 34 is provided.

In addition, the input/output ports 12 and 13 of the microcomputer 1
is connected to the target microcomputer mounting area of the target system 40 via an interface cable 39.

The proxy memory circuit 30 is configured to include a RAM (Random Access Memory) for acting as a data memory and a program memory in the target system 40. The emulation control circuits 28 and 29 control emulation operations based on start conditions and various control conditions for emulation. The breakpoint control circuits 26 and 27 monitor the control state of the microcomputer 1, the states of the emulation buses 22 and 23, and the identification information given from the ID bus 31 and 32, and reach a preset state. When this happens, a break interrupt is generated to break the emulation operation. The trace circuit 24
．． 25 is data and addresses given to emulation buses 22 and 23, as well as control information and ID bus 3.
The identification code given from 1°32 is stored for each successive bus cycle.

Next, an example of emulation operation will be explained.

To start emulation, emulator 2
1, various operating conditions are set according to instructions from the system development device 38. For example, break conditions are set in the breakpoint control circuits 27 and 28, and the CPU modules 2 and 3 included in the microcomputer 1
．． The start address of the program to be executed by the emulation control circuit 28 and 29 are set in the emulation control circuits 28 and 29.

When emulation is started, the target program contained within the target system 40 or held by the proxy memory circuit 30 is executed by the CPU according to a predetermined procedure.
Executed by module 2, 3.4. At this time C
All information such as data and addresses that appear on the internal bus 10.11 due to bus cycles generated by the PU module 2゜3.4 etc. are sent to the trace circuit 2 in bus cycle units.
4.25 and the breakpoint control circuit 27.28. At the same time, the circuit module (CPU module, bus master module) that starts the bus cycle outputs its own identification code to the ID bus 16-17 in synchronization with the bus cycle generation timing, and this information is also transmitted to the trace circuits 24-25 and Breakpoint control circuit 2
Given on 7.28.

As a result, the breakpoint control circuits 26 and 27
Breakpoint control is performed while grasping the type of PU module or path master module, and the trace circuits 24 and 25 accumulate information appearing on the internal bus 10 and 11 in correspondence with the identification code. For example, information generated by the operation of one CPU module 2 that shares the internal bus 1o and information generated by the operation of the other CPU module 3 are distinguished by identification codes. Furthermore, even if the CPU modules 2 and 4 operate in parallel, the information on each internal bus 10.11 is paired with the identification code and stored independently in the trace circuits 24.25.

When the break condition is satisfied and execution of the target program by the microcomputer 1 is stopped, the system development device 38 reads and displays the information accumulated in the trace circuits 24 and 25 so far, and performs software debugging and other operations. Used for system debugging.

According to the above embodiment, the following effects can be obtained.

(1) The evaluation microcomputer 1 uses the internal bus 1 in emulation of the target system 4o.
The emulator 21 receiving this outputs the identification code of the CP, U module 2, 3.
U module 2゜3.4 and path master module 5,6
Breakpoint control can be performed while grasping the type of CPU module 2, 3.4, and path master module 5, 6 for trace results.

(2) The microcomputer 1 has a CPU module 2,
By providing emulator input/output circuits 14.15 for each internal bus 10.11 to which 3.4 is connected, even if the CPU modules operate in parallel, each bus information and identification code can be output in real time.

(3) For each emulator input/output circuit 14.15, trace circuits 24, 25, breakpoint control circuit 26.
By providing the emulator 27 and configuring the emulator 21,
Even if the CPU modules operate in parallel, or even if the CPU modules share individual internal buses, it is possible to obtain necessary information in real time and evaluate the target system 40.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, the internal bus to which the CPU module is connected was explained as being connected to an input/output port that can be released to the target system, but the present invention is not limited thereto; Other bus master modules may be connected to internal buses that are never released to the target system. Furthermore, the target system interface coupled to the target system is not limited to the configuration of the above embodiment in which each internal bus is individualized, but may also be of a multiplex format in which internal buses are selectively connected to the outside. good. Further, the number of CPU modules and the number of internal buses included in the microcomputer are not limited to the above embodiments, and can be changed as appropriate. Further, if there is no substantial problem in system evaluation, path master modules other than the CPU module do not need to output identification information. Furthermore, the circuit module built into the microcomputer is not limited to the above embodiment, but can be modified as appropriate.

Further, the emulator is not limited to a type that includes a built-in control processor, but may also be of a type that uses an evaluation microcomputer for internal control by switching the operating space.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, in the operation of multiple built-in CPU modules, the identification information of the CPU module that has generated the bus cycle can be outputted to the outside, and it is possible to determine externally which module's operation is related to the information for tracking the internal operation status. By doing so, it is possible to control breakpoints while understanding the type of CPU module externally, and it is also easy to associate trace results with CPU modules. This has the effect that it is possible to optimize a microcomputer for evaluating an application system of a large-scale semiconductor integrated circuit integrated into a single chip.

By configuring a microcomputer by providing input/output means capable of outputting tracking information and identification information for each internal bus to which a CPU module is connected, it is possible to output each bus information and identification information even when the CPU modules operate in parallel. It has the effect of being able to output in real time.

By configuring an emulator by providing a trace means and a break means for each input/output means, even if the CPU modules operate in parallel, or each internal bus can be
Even if the U module is shared, it has the effect that necessary information can be acquired in real time and system evaluation can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a microcomputer according to the present invention, and FIG. 2 is a block diagram of an embodiment of an emulator according to the present invention.

Claims (1)

[Claims] 1. A microcomputer used for emulation of a system to be evaluated, which includes a plurality of CPU modules and generates bus cycles along with information for tracking the operation of each CPU module. A microcomputer characterized by having an interface means for outputting identification information of a CPU module to the outside. 2. A microcomputer used for emulation of the system to be evaluated, which includes multiple CPU modules and other bus master modules, and which identifies the module that generated the bus cycle along with information for tracking internal operating status. A microcomputer characterized by having an interface means for outputting information to the outside. 3. A target that is a microcomputer used for emulation of the system to be evaluated, which has multiple built-in CPU modules and can connect all or part of the internal bus to which the CPU modules are connected to the system to be evaluated. interface means, and emulator interface means that allows all internal buses to which the CPU modules are coupled to be connected to an emulator system, and the emulator interface means connects each CPU
A microcomputer characterized by outputting identification information of a CPU module that has generated a bus cycle to the outside together with information for tracking the operation of the module. 4. The emulator interface means is connected to the CP
4. The microcomputer according to claim 3, wherein each internal bus to which the U module is connected has dedicated input/output means. 5. An emulator for emulating a system to be evaluated using the microcomputer according to claim 4, comprising a trace means for sequentially storing input information in synchronization with a bus cycle, and input information and expected value information. A break means for generating a break signal by detecting a match between the input and output means is provided for each input/output means.