JP2570558B2 - Hardware emulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for emulation of hardware. The present invention relates to an emulator that can perform hardware functions in a pseudo manner by software.

[0002]

2. Description of the Related Art An emulator simulates a part of the hardware operation in a circuit to be evaluated when performing device evaluation. In device development, there is a great risk in manufacturing a custom LSI using only a single simulation, and therefore, a system is required that allows the file after the completion of the single simulation to be mounted on a development target device and checked for operation. In addition, when an actually manufactured LSI has an operation failure, it is difficult to analyze the circuit operation inside the LSI while operating on the device without an emulator. .

[0003] Various emulators have been developed from such a development environment.
The circuit to be emulated is FPGA
(Fi-eld Programmable Gate Array), a socket interface 32 having an input / output interface function with the socket 21 on the external device 20, and a test pattern for generating an input pattern to the FPGA emulation module 33. It is composed of a generating unit 36 and a controller 34 that controls the entire system.

Next, the operation of the conventional emulator thus configured will be described.

[0005] The socket 21 is mounted in an external device 20 under development, and the socket 21 and the external device 20 are connected via a cable 311. The signal input from the external device 20 via the socket 21 is input to the socket interface 32, and the test pattern generation unit 36 converts the signal input via the socket interface 32 into F
An input pattern operable on the PGA emulation module 33 is generated. The FPGA emulation module 33 performs an emulation operation according to the input pattern, and the controller 34 controls the whole.

[0006]

[0005] Such a conventional emulator is expensive because it has an emulation module formed of an FPGA therein, and requires a circuit to be emulated to be an FPGA. Has not been easily performed on a workstation.

An object of the present invention is to eliminate such a drawback. An emulator capable of reducing costs by enabling hardware functions to be simulated by software and further shortening the period of device evaluation. The purpose is to provide.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a hardware emulator having means for connecting an external device to be evaluated and for emulating a hardware operation in accordance with an operation input from a terminal and executing emulation. An input interface for converting an input signal from the external device from a voltage level to a logic signal to generate input pattern information, a circuit diagram information memory for storing circuit diagram information to be supplemented, and an input from the input interface emulation processor type the pattern information and information from the circuit diagram information memory, a circuit operation emulation of the output from the emulation processor
Emulation processing for one pattern information
A clock generating circuit for generating a clock signal to be supplied to the external device according to completion timing information, and converting the output signal from the emulation processor and the clock signal from the clock generating circuit from a logical signal to a voltage level to the external device And an output interface for outputting the data to the computer.

An emulation result accumulation memory for accumulating an emulation result and a logic library for accumulating information on a logical operation of a circuit element are provided. The emulation processor reads circuit diagram information to be supplemented from the circuit diagram information memory. Means for executing a logical operation of each element in the circuit diagram information with reference to the information stored in the logic library, and further connected to a terminal device for monitoring an emulation state of the emulation processor. It is desirable to have a terminal interface.

[0010]

The signal from the external device to be emulated is converted into logic signals of "0" and "1" and sent to the emulation processor as an input pattern. The emulation processor controls the event of the circuit element in the circuit diagram information during the execution of the emulation, performs the operation processing of the circuit element based on the input pattern information, and informs the clock generation circuit of the timing of the completion of the emulation processing for one pattern information. Is sent. The clock generation circuit generates a clock signal each time the timing information is received and outputs the clock signal to an external device. This clock signal is synchronized and operated as an execution operation clock of the external device.

Thus, emulation can be performed according to the circuit diagram information while operating the hardware function of the external device, and the analysis of the defect can be performed at low cost and in a short time.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

In the embodiment of the present invention, a hardware emulator for connecting an external device 20 to be evaluated and realizing a hardware operation in accordance with an operation input from the terminal 1 to execute emulation is provided. An input interface 4 for converting input signals of the input signal from a voltage level to a logic signal to generate input pattern information, a circuit diagram information memory 2 for storing circuit diagram information to be supplemented, an input pattern information and a circuit from the input interface 4 An emulation processor 3 for inputting information from the diagram information memory 2 and performing circuit operation emulation; a clock generation circuit 5 for generating a clock signal to be supplied to an external device 20 in accordance with timing information from the emulation processor 3; Output signal from An output interface 6 for converting a clock signal from a clock generation circuit 5 from a logic signal to a voltage level and outputting the converted signal to an external device 20, an emulation result accumulation memory 9 for accumulating an emulation result, and accumulating information on a logic operation of a circuit element. The emulation processor 3 includes a logic library 10 for reading circuit diagram information to be supplemented from the circuit diagram information memory 2, and a logic operation of each element in the circuit diagram information stored in the logic library 10. And a terminal interface 7 to which the terminal 1 for monitoring the emulation state of the emulation processor is connected.

An emulation target circuit is mounted on the external device 20 via a socket 21. The emulation processor 3 is connected to the external device 20 and the terminal 1.

A signal input from the socket 21 mounted on the external device 20 is converted from a voltage level into a logical signal of “0” or “1” by the input interface 4, and is input to the emulation processor 3. Generated as pattern information.

The circuit diagram information memory 2 stores circuit diagram information, and the emulation processor 3 performs event control of circuit elements in circuit diagram information during execution of emulation, arithmetic processing of circuit elements based on input pattern information, and information transfer. In addition to performing communication control, the circuit diagram information memory 2
Emulation operation of the circuit diagram information therein and timing information for the clock generation circuit 5 are generated.

The clock generation circuit 5 generates a clock signal each time it receives timing information indicating completion of emulation processing for one pattern information from the emulation processor 3, and outputs this clock signal to the output interface 6.
To the external device 20 via the. By using this clock signal as the execution operation clock of the external device 20, the external device 20 operates in synchronization. The output interface 6 has an interface function of converting a logic signal for transferring an output signal of the emulation processor 3 and a clock signal generated from the clock generation circuit 5 to the external device 20 to a voltage level.

The terminal interface 7 has an interface function with the terminal 1 such as a workstation, and executes an emulation result analysis, a dump control of an internal signal of a circuit to be emulated, and the like by input from the terminal 1. When analyzing the emulation result from the terminal 1, the emulation result stored in the emulation result storage memory 9 is accessed.

FIG. 2 is a timing chart showing the relationship between the emulation processor and the clock generation circuit in the embodiment of the present invention.

The logical operation of the circuit to be emulated is simply performed as shown in the drawing. At that time, however, there arises a problem that the operation speed of the external device (hardware device) 20 differs from the emulation speed of the emulation processor 3. For example, even if the operation speed of the external device (hardware device) 3 is about 8 MHz,
The emulation speed is about 1 MHz, depending on the performance of the central processing unit 11.

Therefore, the emulation processor 3
Is a clock of the limit speed of the emulation speed (the time from when a signal is applied to an input terminal to calculate logic and a result is output to an output terminal).
The 0 side must be operated. Thus, the clock generation circuit 5 synchronizes the external device 20 with the emulation operation, whereby the external device 20 and the circuit to be emulated operate with the same clock.

FIG. 3 is a flowchart showing the operation flow of the emulation processor in the embodiment of the present invention.

This is an example of the circuit to be emulated shown in FIG. 2. First, circuit diagram information is read from the circuit diagram information memory 2, and the logic library 10 is read out from the gate, flip-flop and the like in the circuit diagram. And link (correspondence). At this time, wiring delay information is added. When a signal is applied from the external device 20, the logic device 10 refers to the logic library 10 including a delay and outputs a logic result of the input signal as an output signal. Next, emulation of block a (AND) and block b (DF) is performed. Thereafter, the next clock cycle is started and the same emulation is performed.

[0024]

As described above, according to the present invention, it is possible to emulate some hardware functions of the device according to the circuit diagram information and to dump the internal signal, and to store the circuit diagram information in the memory. Since the information can be stored in software, the change can be easily performed, and there is an effect that a problem on a circuit inside the LSI when the device is opened can be easily found, dealt with, and immediately reflected in the LSI design.

In the analysis of device operation defects found after the actual LSI chip is manufactured, it is possible to analyze the internal defects of the LSI while operating the device and freely monitor the internal signals on the circuit on the terminal. Since it becomes possible, the apparatus evaluation period can be greatly reduced, and since the emulation operation can be performed by a software configuration, the configuration can be inexpensively configured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing a relationship between an emulation processor and a clock generation circuit according to the embodiment of the present invention.

FIG. 3 is a flowchart showing a flow of an operation of the emulation processor in the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 terminal 2 circuit diagram information memory 3 emulation processor 4 input interface 5 clock generation circuit 6 output interface 7 terminal interface 9 emulation result storage memory 10 logic library 11 central processing unit (CPU) 20 external device 21 socket 30 hardware emulator 32 socket Interface 33 FPGA emulation module 34 Controller 36 Test pattern generator 41, 42, 311 Cable

Claims (4)

(57) [Claims] 1. A hardware emulator comprising means for connecting an external device to be evaluated and realizing a hardware operation in accordance with an operation input from a terminal and executing emulation, wherein an input from the external device is provided. An input interface for converting a signal from a voltage level to a logic signal to generate input pattern information; a circuit diagram information memory for storing circuit diagram information to be supplemented; an input pattern information from the input interface and the circuit diagram information memory An emulation processor that inputs information from the emulator and performs circuit operation emulation, and one emulator output from this emulation processor
A clock generation circuit for generating a clock signal to be supplied to the external device according to timing information of completion of emulation processing for pattern information; and an output signal from the emulation processor and a clock signal from the clock generation circuit being converted from a logic signal to a voltage level. And an output interface for converting and outputting to the external device.
emulator. 2. The hardware emulator according to claim 1, further comprising an emulation result storage memory for storing an emulation result. 3. An emulation processor comprising: a logic library for storing information relating to a logic operation of a circuit element; wherein the emulation processor reads circuit diagram information to be supplemented from the circuit diagram information memory; Means for executing a logical operation of an element by referring to information stored in the logical library. 4. The hardware emulator according to claim 1, further comprising a terminal interface to which a terminal device for monitoring an emulation state of the emulation processor is connected.