JPS59103158A - Debug system of digital signal processing program - Google Patents

Abstract

PURPOSE:To stop the working of a processor having no halt terminal and to realize the insertion and deletion of a debug branch instruction, by giving twice the output instruction for output register to the end of a branch instruction in case an original program is reset after the end of debug. CONSTITUTION:A subject program of debug is stored in a program memory 1, and the next address is given via a contact A of a switch 6 in response to the decoding result of the preceding instruction of an instruction decoding part 3 of a digital signal processing circuit 9. With this address a new instruction code is given to a DSP main body part 5 and executed. At the same time, a debug processing control part 2 is connected to the memory 1 and an external data processing circuit 7 is connected to an output register 4 of the circuit 9. Then the output instruction for register 4 is given twice to the end of the branch instruction when an original program is reset after the end of debug. Thus the working is stopped for the part 5 having no halt terminal, and the insertion and deletion are possible for the debug branch instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a program-controlled digital signal processing circuit (hereinafter referred to as DSP).
A digital signal processing program debugging system that can generate a halt function and realize a debug function by branching even in a DSP that does not have a terminal for realizing a halt function. It is related to the method.

Prior Art and Problems In order to operate a program-controlled DSP, it is necessary that the program be written correctly, but it is inevitable that some errors will occur when creating the program. Therefore, when developing a DSP program, it is essential to perform debugging procedures to discover program errors.

To debug a DSP program, you can usually use the halt function provided in the DSP to stop the program running at a certain step, and then check the output value in an external register. , a method is used in which the location of errors in a program is investigated by knowing whether the operations up to that step are correct or not, and repeating such steps.

Generally, general-purpose DSPs are equipped with a terminal for performing such a halt function, and this can be used to perform program debugging as described above.
A specially manufactured DSP may not have a terminal for realizing a halt function, and therefore, in such a case, the above-described program debugging using the halt terminal cannot be performed.

Conventionally, a method has been used in which the supply of the master clock is stopped at a certain point in order to put a DSP that does not have a dedicated halt terminal into a halt state for the purpose of program debugging. However, in this method, it is difficult to detect the position at which the clock is stopped. For example, a method such as detecting a program execution address is used, but this method is difficult during high-speed operation. However, this method cannot be applied when the DSP operates with a clock that is independent from the outside, especially when the DSP is made of LSI.

OBJECT OF THE INVENTION The present invention attempts to solve the drawbacks of the prior art, and its purpose is to put the DSP in a halt state and use a branch for debugging in a DSP that does not have a terminal for realizing a halt function. The object of the present invention is to provide a program debugging method that allows insertion and deletion of instructions.

Embodiment of the Invention FIG. 1 shows an example of the configuration of a debug system as an embodiment of the invention. In the figure, 1 is a program memory, 2 is a debug processing control section, 3 is an instruction decoding section, 4 is an output register, 5 is a DSP main body, 6 is a switch, 7 is an external data processing circuit, and 8 is a lotus. . Also, the instruction decoding unit 3 is shown surrounded by a broken line. Output register 4. D
The SP main body 5 is usually integrated as a DSP 9 and
This is realized by Sl.

Furthermore, FIG. 2 shows the original form of a program to be debugged and a method of transforming it during debugging.

In FIG. 1, a program to be debugged is stored in a program memory 1.

During operation, switch 6 is turned to the A side, and DSP 9
A new instruction code is read out by passing the instruction decoding section 3 to the next instruction address according to the instruction decoding result of the previous instruction, and is given to the DSP main body section 5 via the instruction decoding section 3 for execution.

In the original program shown in FIG. 2 fat, it is assumed that the original program is debugged immediately after the original instruction is executed up to address . In this case, debugging is performed by inserting some debug statement (for example, to monitor the contents of an internal register) immediately after the address . What is necessary is to change the jump instruction to a jump instruction that branches to , thereby causing the execution program to jump and execute the debug statement at address m''-n.

In order to return to the original program after debugging in this way, as shown in Figure 2 (C), change the +1 address of the program to the instruction of the original program, and then jump to the +1 address again. That's fine. Such program replacement is performed by turning the switch 6 to the B side, giving an address from the debug processing control unit 2, loading instructions, and updating the contents of the block memo January. At this time, if necessary, the λ address of the program may be changed to a jump instruction to perform further deno<lag.

By the way, the DSP must be stopped during the process of replacing the contents of the program memory, but as mentioned above, it is generally difficult to stop the DSP without a halt terminal. Therefore, Fig. 2(b)
As shown at addresses n-2 and n-1, at the end of the debugging process, a numeric instruction to the output register 4 is given twice. Generally, when there is unprocessed data in a register (output register) for outputting data to the outside, when a command to place the next output data in the output register is issued, the DSP will automatically replace the data that has already been placed. Since instruction execution is stopped until it is read out to the outside, the DSP is stopped by being given the numeric instruction twice, and therefore, the required program can be replaced during that time. After the program has been replaced, if the value of the output register 4 is read twice to the external data processing circuit 7 via the bus 8, a read completion notification is input to the output register 4 each time. Program execution is resumed after the second reading is completed, and after the second reading is completed, +
The program jumps to address 1 and then normal operations are performed. Note that, as is clear from the above explanation, it is not necessary that the two input instructions to the output register be performed at consecutive addresses, and it is sufficient that the value of the output register is not read out between them.

As described in detail, according to the program debugging method of the present invention, when there is unprocessed data in an external register to which data should be output, when an instruction to place the next output data in the output register occurs. In a DSP in which instruction execution is suspended until data that has already been set is read out, a memory for storing the program to be debugged is provided outside the DSP, and the instructions for debugging are provided outside the DSP. When branching is done with a program jump instruction and returning to the original program after debugging, a halt state is generated by giving an output command to an external register twice at the end of the branch instruction, so the halt terminal is Even in the case of a DSP that does not have this, it is possible to stop the operation of the DSP and change the program, such as deleting a branch jump instruction necessary for program recovery.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a program debugging system as an embodiment of the present invention, and FIG. 2 is a diagram showing the original form of a program to be debugged and its transformation during debugging. 1-m-program memory, 2-debug processing control unit, 3-instruction decoding unit, 4-output register, 5-DSP main unit, 6-switch, 7-external data processing circuit, 8-bus, 9- Digital Signal Processing Circuit (DSP) Patent Applicant Fujitsu Limited Agent Patent Attorney Gobe Tamamushi (3 others) Figure 1 Figure 2

Claims (1)

[Claims] If a register for outputting data to the outside has unprocessed data and an instruction to place the next output data in that register occurs, the instruction is executed until the data that has already been placed is read out to the outside. In a program-controlled digital signal processing circuit in which the signal processing circuit is stopped, a memory is provided to store the program to be debugged, and a jump instruction is used to branch the program for debugging, and the original program is returned to the original program. debugging of a digital signal processing program characterized in that when returning to the program, a halt state is generated by providing two output instructions at the end of the branch program, thereby making it possible to change the program such as deleting a jump instruction for branching. method.