JP2853774B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller having a function of detecting an abnormal operation in a subroutine program when a sequence program is executed.

[0002]

2. Description of the Related Art Conventionally, in a programmable controller having a function of detecting an abnormality during execution of a subroutine program in a sequence program, a return address of a subroutine stored in a stack area in a central processing unit (CPU) to a main routine. Is referenced for abnormality detection.

[0003]

However, in the conventional device, the storage location of the return address in the stack area is moved (pushed) in order to write other types of information in the stack area. For this reason, when writing other types of information to the stack area, it is necessary to read the return address from the stack area and store it in a general-purpose register, and the capacity of the sequence program is reduced by the number of program instructions instructing this processing. There was a problem that it increased.

[0004] This point will be described in detail with reference to FIG.

FIG. 6 shows an example of a sequence program having two subroutine programs.

When translating an intermediate language sequence program into a machine language executable by the CPU or when the user himself creates an intermediate language sequence program, the subroutine execution instruction PP2 described in the main routine MAIN is executed. Before this, a program instruction PP1 for making a back calculation request by an input / output parameter is inserted.

When the input parameter indicates level on, in a subroutine program to be moved next,
This means that normal data storage is performed in the stack area, that is, the storage position of the stack area at the return address of the subroutine is changed.

After the instructions PP3 and PP7 for storing data in the stack area in the subroutine, on / off of the input parameters is confirmed, and the address of the stack area where the return address of the subroutine is stored is calculated backward. ,
A program instruction for reading the return address of the subroutine and writing it to the general-purpose register (PP4, PP in FIG. 6)
5, PP8, PP9) are inserted.

The operation procedure of the CPU when executing the sequence program shown in FIG. 6 will be described for each program instruction.

Program instruction PP1: Main routine M
AIN executes subroutine SUB1 (CAL
L), an ON input parameter indicating a return address reverse calculation request is set in a register in the CPU.

Program instruction PP2: A known system operation is performed by a subroutine execution instruction CALL SUB, and C
The PU stores the return address of the subroutine SUB1 to the main routine in the stack area 4, and shifts the execution procedure to the subroutine SUB1.

Program instruction PP3: The register Reg. 1
Is stored.

Program instruction PP4: Since the input parameter is set to ON, a positive determination is obtained in this determination processing, and the processing shifts to the address reverse calculation processing of the next program instruction.

Program instruction PP5: The stack area address storing the return address of subroutine SUB1 (that is, the position of reference symbol A in FIG. 7) is calculated backward from the value of the stack pointer, and then the subroutine SUB1 is returned from this address. The address information is read, and the general-purpose register Reg. 0 is saved (see FIGS. 7 and 8).

Program instruction PP6: The return address of subroutine SUB2 is stored in the stack area by the subroutine execution instruction CALL SUB2 (see FIG. 6), and the execution procedure shifts to subroutine SUB2.

Program instruction PP7: The register Reg. 2 is saved (PUSH), so that the register Reg. 2 are stored.

Program instruction PP8: Subroutine SU
Since the return address back calculation request program for B2 is not described, the execution procedure jumps without moving to the back calculation process.

Program instruction PP9: Subroutine SU
To perform error detection processing using the return address of B1,
The general-purpose register Reg. 0 refers to the return address.

As described above, when two subroutines (programs) are executed in a nested manner, in order to know the return address to the main routine in the second subroutine, the program instructions PP1, 3, 4, 8 , 9 must be inserted in the sequence program. Also, as the number of executions of the subroutine on the main program increases, the number of program instructions PP1
Is required.

For this reason, the conventional apparatus has a problem that the capacity of the sequence program increases when detecting the execution error processing of the subroutine.

In view of the above, an object of the present invention is to provide a programmable controller capable of reducing the capacity of a sequence program as compared with the related art and storing a return address of a subroutine. It is in.

[0022]

In order to achieve the above object, the present invention provides a programmable controller having a function of detecting a subroutine execution abnormality.
Storage means for exclusively storing information indicating the return address of the subroutine for detecting the execution abnormality; identification means for identifying the type and content of the first program instruction to be executed described in the sequence program; And a second program instruction instructing storage of a return address of the subroutine is determined in advance, and the first program instruction to be executed is the second program instruction. And writing means for writing the return address to the subroutine indicated by the first program instruction in the storage means when the identification means has been identified.

[0023]

In the present invention, the user simply writes a newly defined subroutine execution instruction in the sequence program, and the return information of the subroutine is automatically written into the storage means by the writing means when the sequence program is executed. .

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a basic configuration of an embodiment of the present invention.

The programmable controller according to the present embodiment is a programmable controller having a function of detecting a subroutine execution abnormality.

In FIG. 1, reference numeral 100 denotes storage means for exclusively storing information indicating a return address of a subroutine for detecting the execution abnormality.

Reference numeral 200 denotes identification means for identifying the type and content of the first program instruction to be executed described in the sequence program.

Reference numeral 300 denotes a second program instruction for instructing execution of a subroutine, and a second program instruction for instructing storage of a return address of the subroutine is determined in advance. When the identification means identifies the instruction as the second program instruction, the writing means writes the return address to the subroutine indicated by the first program instruction in the storage means.

FIG. 2 shows a configuration of a main circuit of the programmable controller in the embodiment of the present invention.

In FIG. 2, a CPU 10 and a user program memory 20 are commonly connected to a bus.

The CPU 10 reads the sequence program stored in the user program memory 20 in units of sequence instructions according to the system program, and executes a sequence operation specified by the sequence instructions by the internal arithmetic circuit 10-1.

When the read sequence instruction is a subroutine instruction, the return address of the subroutine is stored in the stack area 10-2 as in the prior art, and at the same time, the return of the subroutine is performed in the special register area 10-3 according to the present invention. The first address is stored.

The dedicated register area 10-3 operates as the storage means of the present invention.

An execution procedure of a sequence program in such a circuit will be described with reference to FIG.

FIG. 4 shows a system processing procedure executed by the CPU 10, which is stored in the system program memory inside or outside the CPU 10 in advance.

The sequence program to be executed uses the program of FIG. 3 having the same contents as the conventional example, but differs from the conventional sequence program in the following points.

A subroutine execution instruction "CALLS +" subroutine name "" additionally instructing storage of a return address of a subroutine is replaced with a conventional subroutine execution instruction "CAL
L + "subroutine name"", and this new subroutine execution instruction is used in a sequence program when it is desired to detect a subroutine execution abnormality.

In order to execute the sequence program of FIG. 3, the CPU 10 sets the read address indicated by the program counter in FIG. 4 to the start address of the user program memory 20 and reads the start sequence instruction (FIG. 4). Step S10 → S20).

Subsequently, the CPU 10 compares the code of the read sequence command with various sequence commands whose type and contents are determined in advance. By this comparison, a subroutine execution instruction including "CALLS" in the read sequence instruction is identified (step S30). CPU at this time
10 operates as the identification means of the present invention.

In the example of the sequence program shown in FIG. 3, the first sequence instruction is not a subroutine instruction.
The execution procedure of U10 proceeds in the order of steps S30 → S80.
Executed in U10. Next, the program counter is updated and the next sequence instruction is read from the user program memory 20 (steps S90 → S70 → S
20).

When such a process is repeatedly performed and the sequence program of FIG. 3 is executed in the order described in the sequence command, a subroutine execution command "CALLS SUB1" in the main routine is detected in step S30.

The CPU 10 writes a value obtained by adding "1" to the current count value indicated by the program counter in the stack area as a return address of the subroutine (step S4).
0). The return address information of the stack area 10-2 is used when the execution procedure is returned to the main routine after executing the subroutine. Since these processing procedures are well known, detailed description will be omitted.

Next, the CPU 10 stores the return address information in the register Reg. 0 (step S50). At this time, the CPU 10 operates as the writing unit of the present invention. Next, the CPU 10 stores the count value of the program counter on the subroutine SUB1 in the user program memory 20 based on the identification name indicated by the sequence command.
And reads the first sequence instruction of subroutine SUB1 (step S60 → S7).
0 → S20).

The subroutine program SU shown in FIG.
B1 and SUB2 are calculated and executed by the CPU 10 according to the same processing procedure as before (steps S30 → S80 → S90).
→ loop processing of S70 → S20).

Further, in the subroutine SUB2, when performing processing using the return address of the subroutine SUB1, the CPU 10 operates the register Reg. Read 0 and refer to.

The CPU 10 sequentially executes such a processing procedure, and when all the sequence instructions are read and executed from the user program memory 20, one sequence operation is completed (step S70).

As described above, in this embodiment, the user only needs to describe the subroutine execution instruction of "CALLS" for the subroutine for which the return address is to be stored. In this embodiment, the return address of the stack area is not used to detect the execution error of the subroutine as in the related art, so that the process of restoring the return address accompanying the movement of the storage position of the stack area is not required.

The following examples are given in addition to the present embodiment.

1) In this embodiment, the return address of the subroutine is stored in the dedicated register. However, if the processing speed is allowed to delay, the return address is stored exclusively in a general-purpose register in the CPU 10 or an external memory. You may do so.

2) In this embodiment, the identification means is constituted by the CPU 10 executing software (system program). When the sequence instruction is read from the user program memory 20, the content of the sequence instruction is identified by the decoder. You may.

3) In this embodiment, an example is shown in which a new subroutine execution instruction "CALLS" is used in the main routine MAIN. However, it may be used in a subroutine. In this case, as shown in FIG. The return address is stored in the register area 10-3 cumulatively in accordance with the number of branches.

[0053]

As described above, according to the present invention, a subroutine execution instruction to which an instruction to store a return address of a subroutine is added is newly determined, and means for executing this instruction is provided. Thus, it is not necessary to use the return address information of the stack area. As a result, it is not necessary to write a plurality of program processing instructions for restoring the return address information in accordance with the movement of the storage location of the information in the stack area in the sequence program, and the capacity of the sequence program can be reduced more than before. Can be. In addition, the program memory can be reduced in size with the reduction in the sequence program, and the effects of reducing the sequence calculation time can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 3 is a flowchart showing the contents of a sequence program according to the embodiment of the present invention.

FIG. 4 is a flowchart showing an operation procedure of the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a storage example of a register according to the embodiment of the present invention.

FIG. 6 is a flowchart showing the contents of a sequence program in a conventional example.

FIG. 7 is an explanatory diagram showing storage contents of a stack area in a conventional example.

FIG. 8 is an explanatory diagram showing the contents of subroutine-related storage information of a conventional example.

[Explanation of symbols]

 10 CPU 10-1 Arithmetic circuit 10-2 Stack area 10-3 Dedicated register area

Claims (1)

(57) [Claims] In a programmable controller having a function of detecting a subroutine execution error, a storage means for exclusively storing information indicating a return address of the subroutine for detecting the execution error, and a sequence program. Identification means for identifying the type and content of the first program instruction to be executed, and a second program instruction for instructing execution of a subroutine and for instructing storage of a return address of the subroutine. Writing means for writing, in the storage means, a return address to a subroutine indicated by the first program instruction when the identification means identifies the first program instruction to be executed as the second program instruction in advance And a programmable controller comprising: