JPH1139897A - Stored data inspection of digital memory means - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce changes, as much as possible, required for check with a check program when the stored data is changed by changing a check sum adjustment data so that the total sum adding all stored data including the check sum adjustment data written together with the write data. SOLUTION: In the case of checking an error of stored data of EPROM3 with a check program of a personal computer 9 by storing a check sum adjustment data to a digital storing means EPROM storing the control program, checking is made by determining whether the total sum of the stored data of EPROM3 including the check sum adjustment data becomes a constant value or not. When the control program is corrected, the check sum adjustment data is changed to make constant the total sum. Thereby, even if the control program is corrected, it is not required to change the check program of the personal computer 9 and thereby check can be conducted easily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting stored data of digital storage means for inspecting stored data stored in digital storage means by an inspection program.

[0002]

When an inspection program is used to check the presence or absence of a storage error in data stored in, for example, a ROM, which is a digital storage means, a checksum, which is a total sum obtained by sequentially reading and adding the data stored in the ROM, is used. Inspection is often performed using such a method.

For example, when data stored in a ROM is control program data of a microcomputer, etc.,
The control program data is often modified due to a change in specifications, and in some cases, a ROM may be added. Then, since the checksum of the control program data also changes, it is necessary to change the contents of the inspection program accordingly.

As a prior art for minimizing the change required in such a case, Japanese Patent Application Laid-Open No. 57-37797 discloses a conventional technique.
Is disclosed in Japanese Unexamined Patent Application Publication No. 2000-205,878. This is based on the premise that there are a plurality of ROMs and a dedicated ROM that stores only data used for inspection using checksums.
Are separately provided, and the head address, the number of bytes, and the checksum of each ROM are stored, respectively.

However, in this method, any of R
When the OM storage data is changed, the checksum dedicated RO
The stored data of M must also be changed. Also, R
When the number of OMs is increased, the capacity of the dedicated ROM for the checksum becomes larger. Furthermore, for example, when the control target of the microcomputer, that is, the product is different, it is not necessary to change the program for the checksum inspection. However, with the change of the control program, the data stored in the dedicated ROM for the checksum is also changed. Changes need to be made.

The present invention has been made in view of the above circumstances, and an object of the present invention is to minimize a change necessary for performing an inspection by an inspection program when data stored in a digital storage unit is changed. It is an object of the present invention to provide a method for inspecting stored data of digital storage means.

[0007]

According to the storage data inspection method of the digital storage means according to the first aspect of the present invention, when the storage data of the digital storage means is inspected by the inspection program for the presence or absence of a storage error, the data is written together with the write data. A total sum of all stored data including the inserted checksum adjustment data is obtained. Then, the presence or absence of a storage error is determined based on whether or not the sum matches a predetermined constant value.

Therefore, when the storage data of the digital storage means is corrected or new storage data is stored, the checksum adjustment data may be changed so that the sum becomes a constant value. Since the inspection program itself does not need to be changed, the inspection can be easily performed even if the stored data is changed.

According to the storage data inspection method of the digital storage means according to the second aspect, the digital storage means is a rewritable ROM. Therefore, until the storage data is modified and rewritten, such as an EPROM, for example. It can be effectively applied to the case where the contents of the contents stored in a stable state (non-volatile) are checked for the presence or absence of a storage error.

According to the third aspect of the present invention, the stored data of the digital storage means incorporated in the microcontroller or the one-chip microcontroller is inspected. Is changed,
Inspection of the data stored in the digital storage means can be performed easily.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an ECU for controlling an engine of an automobile will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing an electrical configuration of a main part. In FIG. 1, E
The CU (microcontroller) 1 is configured around a CPU (microprocessor) 2 and its CP
U2 is an EPROM (hereinafter simply referred to as ROM) in which a control program (write data) is written and stored.
3 and RAM used as a work area for CPU 2
4 is connected so as to be able to write and read.

At the end of the storage area of the ROM 3, for example, 1
Six bits (one word) of checksum adjustment data are stored. The above contents are stored in the ROM 3 in advance as RO
It is assumed that the data is written in an M writer or the like and then mounted on the ECU 1. The area of the ROM 3 where writing is not performed is set to an initial value (for example, all “F”).

When the CPU 2 obtains information on the engine (not shown) of the vehicle obtained from various sensors via the A / D converter 5 in accordance with the control program read from the ROM 3, the CPU 2 receives the information from the port 6 based on the information. The engine is controlled via the. The timer 7 is a system timer that generates a timer interrupt for the CPU 2 at regular intervals.

Further, a personal computer (hereinafter, referred to as a personal computer) 9 can be connected to the CPU 2 via an interface 8 for serial communication. The A / D converter 5, port 6, timer 7, and interface 8 correspond to peripheral circuits.

The personal computer 9 comprises a main body 9a, a display 9
The main body 9a includes a test program for performing various tests on the ECU 1. And the personal computer 9
The inspection program is executed while communicating with U2.

Next, the operation of this embodiment will be described with reference to FIG. FIG. 2 is a flowchart showing the contents of an inspection program built in the personal computer 9 for inspecting the data stored in the ROM 3 for a storage error.

First, when the inspection program is started in the personal computer 9, the area of the ROM 3 becomes 00000H-1F.
If it is FFFH, the operator is notified to the start address (usually, “0”) and the end address of the area (ROM 3
Since the last (word) access address is 1FFFEH, 20000H) is input from the keyboard 9c. After that, when a command to start the test is input, the flowchart shown in FIG. 2 is executed. It has become so.

In FIG. 2, first, in a processing step S1 of "address counter, accumulator clear", a processor (not shown) built in the main body 9a of the personal computer 9 includes a work area or a register used as an internal address counter. Clears accumulator contents used to accumulate data values to zero. Then, the processing shifts to the processing step S2 of “ROM data reading”.

In step S2, the processor reads one word of the ROM data (stored data) stored in the ROM 3 from the head address via the CPU 2 of the ECU 1. Then, the processing shifts to the next “data value accumulation” processing step S3. In processing step S3, when the processor adds the data of the control program read in step S2 to the accumulator, the processor shifts to the next "address counter / count-up" processing step S4. The bit width of the accumulator is 16 bits.

In the processing step S3, the processor counts up the value of the address counter. In this case, since the ROM data is read in word units, the processor counts up by "2". Then, the processing shifts to the judgment step S5 of “end?”.

In the judging step S5, the processor judges whether or not the processing is to be finished based on whether or not the value of the address counter matches the area end address of the ROM 3.
If the determination is "NO", the flow shifts to step S2 to read the next ROM data according to the value of the address counter.

That is, in the judgment step S5, steps S2 to S5 are performed until the processor judges "YES".
Is repeated, the control program data in the ROM 3 is sequentially read word by word and added to the accumulator. Then, when the accumulation of the data values up to the last area address is completed, at that time, the checksum data which is the sum total of the ROM data is obtained.

However, when the total sum of the control program data overflows the bit width (16) of the accumulator, the portion is truncated, and only the portion indicated by the bit width of the accumulator becomes the checksum data.

Here, for example, the sum of the ROM data is 5
Assuming that AA5H is normal,
This will be described below. In decision step S5, the processor sets "Y
Immediately before determining “ES”, the count value of the address counter is the last access address (1FFFE) in the ROM 3.
H), and at this time, the program data read in step S2 is checksum adjustment data. In step S3, if the accumulated value excluding the checksum adjustment data in the accumulator is 3AA5H,
The checksum adjustment data is 2000H. Therefore, the total sum of the accumulated value excluding the checksum adjustment data and the checksum adjustment data is 5AA5H.

In the next step S4, "2" is added to the address counter, and the value of the counter becomes 20000H, indicating the area end address. Then, the next step S
At 5, the processor determines "YES",
The process proceeds to the judgment step S6 of "matching of matching result?"

In the judgment step S6, the processor compares the test value 5AA5H stored in advance with the contents of the accumulator to judge whether or not they match. If they match, the processor determines "YES" and shifts to the "normal output" processing step S6a.
In this case, it is determined that there is no storage error in the data stored in the ROM 3 and that the data is normal, and the fact is displayed on the display 9b, and then the processing is terminated.

If it is determined in step S6 that the test value stored in advance does not match the contents of the accumulator, the processor makes a "NO" determination and shifts to "abnormal output" processing step S7. In this case, RO
It is determined that the storage data of M3 has a storage error and is abnormal, and the fact is displayed on the display 9b, and then the processing is terminated.

Thus, for example, if the contents of the control program are modified, the contents of the checksum adjustment data are also changed accordingly, and the sum of the ROM data is changed to the inspection value 5A.
A5H. For example, if the value of the checksum data of the ROM data excluding the corrected checksum adjustment data is 4AA5H, the value of the checksum adjustment data may be 1000H. And ROM
The inspection of the stored data of No. 3 can be similarly executed according to the flowchart of FIG.

As described above, according to this embodiment, the ECU 1
The checksum adjustment data is stored in the ROM 3 in which the control program of the CPU 2 built in the ROM is stored.
When the presence or absence of the storage error of the storage data of the OM 3 is checked by executing the check program of the personal computer 9, the presence or absence of the storage error is determined based on the total 5AA5H of the ROM data including the checksum adjustment data 2000H.

Therefore, if the checksum adjustment data is also changed at the same time as the control program is corrected, the inspection program itself of the personal computer 9 does not need to be changed, and therefore, even if the data stored in the ROM 3 is changed. As a result, necessary changes can be minimized, and the inspection can be performed easily.

The EPROM 3 stores the written data in a nonvolatile and stable state.
The application of this embodiment is effective for checking the presence or absence of a storage error in the ROM 3.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. The present invention is not limited to the case where a part of the control program is modified, and is applicable even when the entire control program is newly rewritten. In other words, even if the control target of the microcontroller is different from that of an automobile engine (for example, home appliances, audio, medical equipment, computer peripherals, and the like), it can be applied without changing the inspection program. Further, the digital storage means is not limited to the one built in the microcontroller, but may be any one used in a system using another CPU. The write data is not limited to the control program but may be another program or data.

The checksum adjustment data is not limited to the data arranged at the end of the ROM 3, but may be arranged at any address within the area of the ROM 3. The digital storage means is not limited to the EPROM 3, but may be an EEPROM, an OTPRO.
M or a flash ROM may be used. The present invention is not limited to ROM, and the present invention may be applied as storage data using known data written in SRAM or DRAM. When accumulating the data values of the control program, the data values may be accumulated in byte units or long words (32 bits). In that case, to increment the address counter in step S4, it is sufficient to add +1 or +4. The inspection program may be arranged in the ROM 3 and executed by the CPU 2. In this case, the inspection result can be notified to the outside.

Even if additional ROMs are added, each ROM is checked by inputting its start address and area end address. Alternatively, if each area is set to be continuous, the inspection can be performed collectively by giving the area end address of the last ROM. Also, RO
When M is added, the checksum adjustment data is also provided in the added ROM, so that even if the contents are changed, it is possible to correct each ROM. E
The CU1 may be a one-chip microcontroller in which all elements are configured on one chip.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an electrical configuration of the present invention.

FIG. 2 is a flowchart showing the contents of an inspection program.

[Explanation of symbols]

1 is an ECU (microcontroller), 2 is a CPU, 3
Denotes an EPROM (digital storage means), 4 denotes a RAM, 5 denotes an A / D converter (peripheral circuit), 6 denotes a port (peripheral circuit), 7 denotes a timer (peripheral circuit), and 8 denotes an interface (peripheral circuit).

Claims (4)

[Claims] 1. A method for checking the presence or absence of a storage error of storage data stored in a digital storage means using a test program, wherein when writing and storing write data in the digital storage means, The checksum adjustment data in which the sum of all the storage data including the data becomes a predetermined constant value is written and stored in the digital storage means together, and by executing the inspection program, all the data stored in the digital storage means are stored. A storage data inspection method for digital storage means, wherein a total sum of storage data is obtained, and when the total does not match the predetermined value, a storage error is determined. 2. The method according to claim 1, wherein said digital storage means is a rewritable ROM. 3. The digital storage means according to claim 1, wherein said digital storage means is incorporated in a microcontroller including a microprocessor (CPU), a RAM, and peripheral circuits. Storage data inspection method. 4. The method according to claim 3, wherein the microcontroller is formed of a single chip.