JP2907114B2 - Method and apparatus for correcting 1-bit error in EEPROM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 1-bit error correction method for a storage device of an information processing apparatus, and more particularly to an EEPRO
The present invention relates to a 1-bit error correction method and apparatus capable of verifying and correcting a 1-bit error of data stored in an M device by comparing it with an error verification value.

[0002]

2. Description of the Related Art Various methods and apparatuses have been disclosed and proposed for the above-mentioned one-bit error correction system. For example, Japanese Patent Application Laid-Open No. 7-129424 discloses that
A circuit having an error detection and correction (ECC) function detects a 1-bit error in output data from the memory circuit and notifies the CPU of detection information to be output when a predetermined mode is set. Is notified to the CPU to prevent the system from going down due to the occurrence of an uncorrectable error of 2 bits or more.
A 1-bit error detection and notification device for a C function circuit is disclosed.

Japanese Patent Laid-Open Publication No. Hei 6-324894 discloses that, in order to automatically correct a one-bit error in memory data of a computer, a parity bit is set every several bits of data when data is written from a processing unit to a memory. A plurality of parity bit addition circuits to be added, a parity bit memory for storing the parity bit data from the plurality of parity bit addition circuits, and a parity check are performed by reading the parity bit data and the memory data from the parity bit memory. A computer error correction circuit comprising a parity check / data correction circuit for automatically correcting a 1-bit error is disclosed.

[0004]

As described above, the conventional one-bit error correction means detects and corrects a bit error occurring on a data bus when reading data from an operating memory. It is.

However, in a large-scale information processing apparatus, requirements such as durability against an operating environment such as high temperature and humidity change are extremely severe, and bits of a ROM device may change during operation.

Conventionally, in order to detect a bit change of such a ROM device, especially an EEPROM at the time of start-up of the device, a CRC code which is an error verification value added to the end of data stored in the EEPROM, Or, compare the error verification value of the same level with the verification value calculated by reading all data at system startup, and
Although the validity of the PROM was verified, if an error was detected, the confirmation of the error occurrence position was not performed.

Accordingly, when an error is detected, the EEPROM
And the system must be brought down to replace the EEPROM.

An object of the present invention is to solve the above-mentioned problems,
An EEPROM 1-bit error correction method and apparatus capable of verifying the validity of an EEPROM storing data including a program in an information processing device at system startup and correcting a detected 1-bit error is disclosed. To provide.

[0009]

According to the 1-bit error correction method of the present invention, a natural number temporary number excluding 2 n is sequentially assigned to each bit from the first bit of the data to the last bit of the data. It is checked whether the value is “1” one bit at a time from the first bit of the data, and a temporary number indicating the position of the bit whose value is “1” and an initial value “0” The exclusive OR with the calculated value of the m-bit bit error is calculated as the calculated value of the next bit error up to the last bit of the data, and added to the calculated value of the last bit error of the data and the data The calculated exclusive OR of the two values is compared with the calculated error verification value, and the value of the exclusive OR between the calculated value of the last bit error and the error verification value added to the data is “0”. Check whether it is not, error check value and error verification value Exclusive rather than the value of the logical sum is "0", and, if not also power of 2 n corrects rewrites the 1-bit value corresponding to the temporary number of the value.

A 1-bit error correction apparatus according to the present invention comprises a bit error calculation value holding unit having the same number of bits as an error verification value added to data and having an initial value set to "0";"1" bit detecting means for detecting the bits of the value "1" in order from the last bit to the last bit, the value held in the bit error calculation value holding unit, and "1" detected by the "1" bit detecting means Calculating means for sequentially calculating the exclusive OR with the value indicating the position of the bit, and storing the result in the bit error calculation value holding unit; and calculating the bit error after completing the calculation up to the last bit of the data. Error bit position detection means for calculating the exclusive OR of the value held in the calculated value holding unit and the error verification value added to the data to detect the position of a bit having a bit error; Detection of detection means And a bit correction means for correcting the bit position.

The position of each bit of the data used by the calculating means is, in order from the first bit to the last bit of the data, 2 n, where n is a natural number of 0 or 1 or more,
It is desirable that a natural number other than the number represented by is assigned.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention, and FIG. 2 is a flowchart showing an operation procedure of the embodiment of FIG.

In FIG. 1, a 1-bit error correction device according to the present embodiment includes a rewritable ROM for storing program codes and data, that is, an EEPROM 1 and an EEPROM.
From the first bit to the last bit of the data stored in the ROM 1, a temporary number assigning unit 21 for assigning a temporary number in which each bit is assigned a natural number excluding 2 to the power of n and a temporary number of a bit whose value is "1" , A bit error calculator 2 comprising an exclusive OR calculator 22 for sequentially calculating a bit error verification value as an exclusive OR, and the bit error verification value calculated by the calculator 2 and the last of the data stored in the EEPROM 1. The exclusive OR of the two is calculated by comparing the value with the error verification value added to the tail. If the value is not "0" and not 2 to the power of n, a bit having the value as a provisional number And an error bit correction unit 3 including a correction unit 32 that corrects the one-bit error of the provisional number determined by the error bit position detection unit 31.

The operation of the 1-bit error correction device is shown in FIG.
(A) First, the value E (n) of the bit error verification value calculation unit 2
Are set to 0, and an initial value E (0) is set. (B) Next, the first bit of the data stored in the EEPROM 1 is read, and it is determined whether the value is “0” or “1”. If the value is determined to be “1”, a temporary indicating the position of the bit is determined. The exclusive OR of the number and the error verification value E (0) is calculated, and the calculated value is set as a calculated value E (1).

This provisional number is 2 n (n = n) for each bit from the first bit to the last bit of the data.
0, 1, 2,. . . ), Ie, 1, 2, 4,
8. . . 3,5,6,7,
9,. . . Etc. are allocated in order.

Therefore, if the first bit is 1, the initial value E (0) of (000 ... 00) and the provisional number of the first bit "3", that is, (000 ... 11), (000 ... 11) of the exclusive OR is the calculated value E (1) of the bit error, and if the value of the first bit is "0", the initial value E (0) = 0 is directly used for the next error calculation. Value E
(1). (C) Next, the second bit is read and similarly determined whether it is "0" or "1". (D) If it is determined to be "1", the provisional number "5" is mistaken. The exclusive OR of the calculated value E (1), that is, “0” or “3”, is calculated, and the calculated value is calculated as the calculated value E of the next error.
(2). When the read second bit is determined to be “0”, the error calculation value E of the first bit is calculated.
(1) is used as the second error calculation value E (2) as it is. (E) Thereafter, similarly to (c) to (d), the determination of the bit value “0” or “1” and the exclusive operation of the temporary number of each bit and the error calculation value E (n) are performed. The procedure for calculating the logical sum is repeated until the last bit, an error calculation value E (N) of the last bit of the data is obtained, and the error calculation value E (N) of the last bit is sent to the error correction unit 3. . (F) The error correction unit 3 calculates an exclusive OR of the error verification value P added to the end of the data and the value E (N) obtained by the calculation, and the calculation result is expressed by all bits. It is determined whether it is not “0”.

That is, if the calculation result is all bits “0”, the verification is terminated assuming that the validity of the data has been verified, and the calculation result is not “0” and one or more bits are “0”. If "1", it means that a one-bit error has been detected. (G) If a one-bit error is detected,
The value of the exclusive OR of the two error verification values P and the calculated value E (N) is 2 n (n = 0, 1, 2,...), That is, only one bit among all bits Only whether it is "1" is checked.

If two error verification values P and calculated values E
The value of the exclusive OR of (N) is 2 n (n = 0, 1,
2,. . . ), The detected 1-bit error exists in the error verification value P added to the end of the data, and thus the validity of the data is verified. After the verification is completed, the process proceeds to (h), and the program of the data is started. (H) If the value of the exclusive OR of the error verification value P and the calculated value E (N) is not “n, n” (n = 0, 1, 2,...) In this case, the detected 1-bit error exists in the data, and the value of the exclusive OR represents a temporary number indicating the position of the bit where the 1-bit error is detected. The bit at the position corresponding to the provisional number is rewritten and corrected to "1" if it is "0" and to "0" if it is "1". (I) When the above operation is completed, the validity of the data is verified or a one-bit error has been corrected, and the program is started using the data.

[0020]

As described above, according to the present invention, the position of each bit of data is represented by a natural number temporary number excluding 2 to the n-th power from the first bit of the data. By adding the provisional number assigned to the bit of the value as an exclusive OR and rewriting sequentially, and finally calculating the exclusive OR of the value of this error verification calculation unit and the verification value added to the data, At the time of system startup, it is easy to verify the validity of the EEPROM and to correct a 1-bit error, so that the system can be started quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 2 is a flowchart showing an operation procedure of the embodiment of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 EEPROM 2 Calculating part of bit error verification value 21 Provisional number assigning part 22 Exclusive OR calculating part of provisional number 3 Error bit correcting part 31 Error bit position detecting part 32 Correcting part

Claims (3)

(57) [Claims] 1. A 1-bit error correction method for an EEPROM in which data including a program and a plurality of m-bit error verification values added to the data are stored. In order 2
Is a natural number excluding the nth power of n, where n is a natural number of 0 or 1 or more, and is assigned with a m-bit number, and is examined one bit at a time from the first bit of the data.
Detecting the provisional number assigned to the bit whose value is “1”; and setting the detected provisional number and the bit error calculation value, where the initial value of the bit error calculation value is all m bits to “0”;
And rewriting the result as the next bit error calculation value. The rewriting of the bit error calculation value is sequentially repeated every time a bit of “1” is detected, and Execute to the last bit, and when the detection and rewriting to the last are completed, calculate the exclusive OR of the rewritten bit error calculation value and the error verification value added to the data. Checking whether the value of the exclusive OR of the bit error calculation value and the error verification value is not “0”; and determining that the value of the checked exclusive OR is not “0”;
A one-bit error correction method for an EEPROM, wherein the value of the bit corresponding to the provisional number having the same value as the value of the exclusive OR is rewritten if the value is not the nth power of the EEPROM. 2. An E which stores data including a program and a plurality of m-bit error verification values added to the data.
A 1-bit error correction device for EPROM, comprising: a calculated value holding unit having the same number of bits as an error verification value added to the data, and having an initial value set to “0”; "1" bit detecting means for sequentially detecting the bits of the value "1" up to the bit of "1", the value held in the calculated value holding section, and the bit in which "1" is detected by the "1" bit detecting means. Calculating means for sequentially calculating an exclusive OR with a value indicating the position of the data, and holding the result in the calculated value holding unit; and holding the result in the calculated value holding unit after completion of calculation up to the last bit of data. An error bit position detecting means for calculating an exclusive OR of a value and an error verification value added to the data to detect a position of a bit having a bit error; and a position detected by the error bit position detecting means. Bit E characterized by having a bit correction means for correcting the
EPROM 1-bit error correction device. 3. The position of each bit of data used by the calculating means is a number represented by 2 n raised from the first bit to the last bit of the data, where n is 0 or a natural number of 1 or more. 3. The one-bit error correction device for an EEPROM according to claim 2, wherein a natural number excluding, is assigned.