JP4135413B2 - MEMORY CHECK SYSTEM, MEMORY CHECK METHOD, SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING DEVICE MEMORY CHECK METHOD, AND MEMORY CHECK PROGRAM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory check system, a memory check apparatus and method for checking data and programs stored in a memory, and a memory check program.
[0002]
[Prior art]
Conventionally, a DSP (Digital Signal Processor) is often used to perform signal processing using, for example, a digital filter. The DSP configures an arithmetic unit that performs addition / subtraction / division based on a program (instruction) or coefficient data stored in a ROM (Read Only Memory) or RAM (Random Access Memory), and performs signal processing on the input digital signal. Have been to do. In particular, DSPs of the type that store programs and coefficient data in the RAM are in great demand in recent years because the functions of the DSP can be flexibly changed by rewriting the stored contents of the RAM. In such a DSP, for example, instruction data and coefficient data are generally downloaded from a microcomputer controlling the DSP and stored in the RAM.
[0003]
The DSP has an instruction RAM in which program code is stored and a coefficient RAM in which coefficient data is stored, and these are connected by a bus. In addition, the RAM is an instruction RAM and a coefficient RAM, and further, for example, a RAM for storing X coefficient data and a RAM for storing Y coefficient data are physically independent of each other, and a bus connected to each RAM is also provided. Each is physically independent.
[0004]
As a result, the DSP can read and write data in each RAM in parallel. For example, the X coefficient and the Y coefficient are read from the RAM and processed, and the calculation result is temporarily stored in the RAM. A series of processing can be executed with one command. On the other hand, in a configuration using a CPU (Central Processing Unit), the CPU and the RAM are generally connected by a single bus, and in order to perform the above-described processing, each coefficient data is read, arithmetic processing, A plurality of commands corresponding to the respective processes such as storage of arithmetic processing results in the RAM are required. Therefore, the DSP can operate at a higher speed than the CPU with respect to processing centering on the product-sum operation.
[0005]
Data stored in the RAM may be partially destroyed by the influence of static electricity or noise. Also, if an error occurs during writing, such as when the timing does not match when writing data to the RAM, incorrect data will be stored. In addition, there is a bug in the program itself, and the RAM area may be destroyed during the execution of the program. When a DSP program or coefficient data is stored in the RAM and the DSP is used, if there is an error in the contents stored in the RAM, the DSP may not perform an expected operation, and the DSP may run away.
[0006]
[Problems to be solved by the invention]
Therefore, conventionally, several methods have been considered for detecting a DSP runaway or checking the contents stored in the RAM. As an example, there is known a watchdog timer that detects an abnormal loop or runaway of a program by resetting a program counter every certain period. According to this, it is possible to detect, for example, when the program counter indicating the execution location of the program is abnormal.
[0007]
As another example, in Japanese Patent Laid-Open No. 5-313908, a program abnormality detection program for detecting an abnormality in an execution program is stored in an external memory in advance, and this program abnormality detection program is used. A method for detecting errors on the RAM is disclosed. The program abnormality detection program is downloaded from the external memory to the RAM together with the execution program. With this program abnormality detection program, the execution program on the RAM and the program abnormality detection program are checked for abnormality, and the execution program and the program abnormality detection program in which the abnormality is detected are corrected.
[0008]
For example, the program abnormality detection program obtains a checksum or XOR for program data or coefficient data stored in the RAM, and obtains the obtained value and a check code such as a correct checksum value or XOR result prepared in advance. By comparing, program and data are inspected.
[0009]
However, in this method, access is performed in units of RAM addresses, and after reading the data stored in the RAM, the read data is transferred to an error detection program or error detection means to detect errors. For this reason, when a large amount of data and program code can be easily processed as the processing capacity of the CPU and DSP is improved, the capacity of the RAM that must be checked increases, and a great deal of time is spent on the check time. There was a problem that it had to be.
[0010]
In this method, the program abnormality detection program and check code for detecting a program abnormality, and the execution program and coefficient data to be detected exist on the same RAM. For this reason, there is a problem that the program abnormality detection program and the check code stored in the RAM or the execution program and the coefficient data may be destroyed due to the influence of static electricity or the like.
[0011]
As another example, Japanese Patent Laid-Open No. 2000-339230 discloses that information stored in a RAM is transferred to an error detection unit directly using DMA (Direct Memory Access), and the contents stored in the RAM are erroneous. A method for determining whether or not is included is disclosed. According to this method, it is possible to detect not only program data stored in the RAM but also error such as coefficient data stored in the RAM. Therefore, it is possible to detect a data error that does not cause the DSP or CPU that operates based on the data stored in the RAM to run away.
[0012]
Further, according to the method disclosed in Japanese Patent Laid-Open No. 2000-339230, it is not necessary to execute a detection program on the CPU when detecting an error such as program data or coefficient data stored in the RAM. There is an advantage that it is not necessary to estimate the CPU processing capacity excessively in consideration of data error detection. Further, since the error detection means is provided separately from the RAM, even if the RAM contents are destroyed, the error detection itself is performed without any problem.
[0013]
However, this method also has the problem that the check time increases as the RAM capacity increases as described above.
[0014]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory check system, a memory check device and method, and a memory check program capable of checking and correcting program data and coefficient data stored in a RAM at high speed and accurately. There is.
[0015]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a rewritable memory of a signal processing apparatus having a rewritable memory and performing signal processing according to the contents written in the rewritable memory. A memory check system for checking contents includes a memory for storing an execution program, a parity check program, and a parity code obtained as a result of performing a parity operation on the execution program and the parity check program using the parity check program Based on the execution program stored in the rewritable memory, which has a rewritable memory connected to the host device and connected to the host device for storing the execution program, parity check program and parity code supplied from the host device Signal for signal processing And a signal processing device that uses a parity check program stored in a rewritable memory to rewrite the unit address of the rewritable memory for the execution program and parity check program stored in the rewritable memory. The memory check system is characterized in that a parity calculation is performed for each block having a plurality of sizes and a detection code based on the result of the parity calculation is output.
[0016]
The present invention also provides a host device having a memory for storing an execution program, a parity check program, and a parity code resulting from performing a parity operation on the execution program and the parity check program by the parity check program A signal processing device that has a rewritable memory for storing an execution program, a parity check program, and a parity code supplied from a host device, and performs signal processing based on the execution program stored in the rewritable memory In the memory check method for checking the contents of rewritable memory, The signal processor An execution program supplied from a host device having a memory for storing an execution program, a parity check program, and an execution program and a parity code obtained by performing a parity operation on the parity check program in the parity check program The parity check program and the parity check program stored in the rewritable memory for storing the parity code are used to change the unit address of the rewritable memory to the execution program and parity check program stored in the rewritable memory. A parity operation step for performing a parity operation for each block of a plurality of sizes; The signal processor And a detection code output step for outputting a detection code based on the result of the parity operation in the parity operation step.
[0017]
The present invention also provides an execution program, a parity check program, and a parity in a signal processing apparatus having a rewritable memory and performing signal processing according to the contents written in the rewritable memory. A rewritable memory that stores the parity code that is the result of performing parity operation on the execution program and the parity check program in advance by the check program, and signal processing based on the execution program stored in the rewritable memory Signal processing means for performing, The signal processor Parity calculation for each block of multiple rewritable memory unit addresses for the execution program and parity check program stored in the rewritable memory using the parity check program stored in the rewritable memory And a detection code based on the result of the parity operation is output.
[0018]
Further, the present invention relates to a memory check method for a signal processing apparatus having a rewritable memory and configured to perform signal processing according to the contents written in the rewritable memory. The signal processor Parity check program stored in a rewritable memory that stores an execution program, a parity check program, and a parity code resulting from performing a parity operation on the execution program and the parity check program in advance by the parity check program A parity calculation step for performing a parity calculation for each block of a plurality of sizes of unit addresses of the rewritable memory for the execution program and parity check program stored in the rewritable memory; The signal processor And a detection code output step for outputting a detection code based on the result of the parity calculation in the parity calculation step.
[0019]
The present invention also provides a memory check that has a rewritable memory, and that performs a memory check on the rewritable memory of a signal processing device configured to perform signal processing according to the contents written in the rewritable memory. In the program The signal processor The execution program, the memory check program for checking the memory by parity operation, and the parity code resulting from performing the parity operation on the execution program and the memory check program in advance are stored in a rewritable memory and can be rewritten. Parity calculation step for performing parity calculation for each block having a plurality of rewritable memory unit addresses for the execution program and the memory check program on the memory; The signal processor And a detection code output step for outputting a detection code based on the result of the parity calculation in the parity calculation step.
[0020]
As described above, the invention described in claims 1 and 7 includes an execution program, a parity check program, and a parity code as a result of performing a parity operation on the execution program and the parity check program using the parity check program. A host device having a memory for storing data, and a rewritable memory connected to the host device for storing an execution program, a parity check program and a parity code supplied from the host device, and stored in the rewritable memory A signal processing device that performs signal processing based on the executed execution program, and the signal processing device uses the parity check program stored in the rewritable memory to execute the execution program and parity check stored in the rewritable memory. Program On the other hand, the parity calculation is performed for each block of a plurality of sizes of unit addresses of the rewritable memory, and the detection code based on the result of the parity calculation is output, so the time required for the memory check is reduced. In addition, the execution program check and the parity check program itself can be alternately checked.
[0021]
The inventions according to claims 8 and 13 store an execution program, a parity check program, and a parity code obtained as a result of performing a parity operation on the execution program and the parity check program in advance by the parity check program. A rewritable memory and signal processing means for performing signal processing based on an execution program stored in the rewritable memory, and the parity check program stored in the rewritable memory makes the rewritable memory For the stored execution program and parity check program, a parity operation is performed for each block having a plurality of rewritable memory unit addresses, and a detection code based on the result of the parity operation is output. Because the memory With the time required for Ekku is shortened, it is possible to perform the checking check and parity check program itself of the execution program alternately.
[0022]
A memory check program according to a fourteenth aspect of the present invention includes an execution program, a memory check program for checking a memory by a parity operation, a result of performing a parity operation on the execution program and the memory check program in advance. Parity code is stored in a rewritable memory, and parity is performed on each rewritable memory unit address block for the execution program and memory check program on the rewritable memory. Since it has an operation step and a detection code output step for outputting a detection code based on the result of the parity operation in the parity operation step, the time required for the memory check is reduced and the execution program check and Own and check can be performed alternately.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described. In the present invention, an execution program and coefficient data used in a DSP (Digital Signal Processor) are downloaded from a memory of a host microcomputer (hereinafter referred to as a host microcomputer) to a DSP RAM (Random Access Memory), In a configuration in which data is stored in the DSP's RAM, a parity check program that checks the execution program and data downloaded and stored in the DSP's RAM by parity calculation is downloaded to the DSP's RAM together with the DSP execution program and data. On the DSP side, the execution program and coefficient data stored in the RAM and the parity check program itself are checked using the downloaded parity check program.
[0024]
At this time, according to the present invention, the execution program and the parity check program stored in the RAM are checked by the parity check program for each block having a plurality of RAM unit addresses.
[0025]
Since the execution program, the coefficient data, and the parity check program are checked in units of a predetermined size block, the time required for the check can be shortened. Further, since the parity check program itself is also checked in units of blocks, the execution program, coefficient data, and parity check program stored in the RAM can be checked alternately for each block. Thereby, it is possible to always check whether the parity check program itself is normal or not.
[0026]
Further, according to the present invention, the check program stored in the memory on the host microcomputer side is used to check the execution program and coefficient data downloaded to the DSP side and stored in the RAM, and the check program is checked to a predetermined size block. It is done in units. Since the check is performed on both the DSP side and the host microcomputer side, it is possible to determine which of the check code used for the check and the check program is not normal.
[0027]
FIG. 1 schematically shows a configuration of an example of a DSP system applicable to an embodiment of the present invention. The host microcomputer 1 is a microcomputer having, for example, a CPU 10 and a memory 11 including a RAM and / or a ROM (Read Only Memory). The DSP 2 has a RAM 20 and operates based on an execution program and coefficient data stored in the RAM 20. The DSP2 execution program is described by instruction codes that can be decoded by the DSP2.
[0028]
The host microcomputer 1 and the DSP 2 are connected by an address bus 3 and a data bus 4. For example, a command for instructing the operation of the DSP 2 is transmitted from the host microcomputer 1 to the DSP 2 via the buses 3 and 4, and the DSP 2 is controlled by the host microcomputer 1.
[0029]
The memory 11 of the host microcomputer 1 stores in advance a DSP program 12, which is an execution program for the DSP 2, coefficient data (not shown), and the like. The DSP program stored in the memory 11 of the host microcomputer 1 is also described using the instruction code described above. Hereinafter, the DSP program and coefficient data used in the DSP program are collectively referred to as a DSP program.
[0030]
A DSP program is uploaded from the host microcomputer 1 to the DSP 2 and stored in the RAM 20 of the DSP 2. For example, the address of the RAM 20 is designated from the host microcomputer 1 to the DSP 2 via the address bus 3. A DSP program is uploaded from the host microcomputer 1 to the DSP 2 via the data bus 4. The uploaded DSP program is written into the RAM 20 based on the address designated using the address bus 3.
[0031]
The DSP 2 performs an operation according to the DSP program downloaded from the host microcomputer 1. By changing the contents of the DSP program uploaded from the host microcomputer 1 to the DSP 2, it is possible to cause the DSP 2 to perform different processes.
[0032]
Further, in the memory 11 of the host microcomputer 1, a parity check program 13 for performing a parity check of the DSP program 12 uploaded to the DSP 2 and stored in the RAM 20, and the DSP program 12 and the parity check program 13 stored in the memory 11. The parity code 14 which is the result of performing the parity operation in advance using the parity check program 13 is stored. The parity check program 13 is described by the above instruction code so that it can be executed in the DSP 2. The parity check program 13 and the parity code 14 are uploaded from the host microcomputer 1 to the DSP 2 together with the above-described DSP program 12 and stored in the RAM 20.
[0033]
FIG. 2 shows an example data arrangement in the RAM 20. In the example of FIG. 2, the RAM 20 has a capacity of 64 kB (kilobytes), and addresses are designated by “0x0000” to “0x10000”. In the address description, “0x” indicates that the description is in hexadecimal notation. Addresses “0x0400” to “0xAFFF” store the DSP program 23. Addresses “0xB000” to “0xFFFF” are the buffer area 24. The buffer area 24 is an area used when the DSP program 23 operates in the DSP 2, and its contents are changed as the DSP program is executed.
[0034]
Addresses “0x0000” to “0x02FF” store the parity code 21. Addresses “0x0300” to “0x03FF” store the parity check program 22. The parity code 21 is a parity code for data in all areas except for the buffer area 24 in the RAM 20. That is, the parity code 21 corresponds to the result of performing a parity operation in advance using the parity check program 22 on the data in all areas except the buffer area 24 of the RAM 20. Since the contents of the buffer area 24 change as the DSP program is executed as described above, the parity is not fixed.
[0035]
Note that the capacity of the RAM 20 is not limited to 64 kB, and the address arrangement shown in FIG. 2 is merely an example, and is not limited to this example.
[0036]
In the present invention, the parity check calculation by the parity check program 22 is performed for each block in units of blocks of a predetermined size. For example, one block is configured with a size in which a plurality of unit addresses in the RAM 20 are collected. As an example, a block having a size corresponding to an area in which the parity check program 22 is stored is defined as one unit block. In this example in which the capacity of the RAM 20 is 64 kB and the parity check program 22 has an address width “0x0100”, a block having a size of 256 bytes corresponding to the address width “0x0100” is defined as one unit block. Therefore, in the example of FIG. 2, the parity code 21 is composed of 3 blocks and the DSP program 23 is composed of 172 blocks.
[0037]
The parity check calculation by the parity check program 22 is performed for each block with one block having a size of 256 bytes as a unit. The parity code 21 that is calculated in advance and stored in the RAM 20 is also one in which the DSP program 23 and the parity check program 22 are subjected to a parity operation in units of the one block. By designating an address to the RAM 20 in a predetermined manner, a parity code corresponding to a block-unit parity operation can be extracted from the parity code 21.
[0038]
In the above description, the block size is the same as the size of the parity check program 22, but this is not limited to this example. The block size can be arbitrarily set in the addressing unit of the RAM 20. For example, the block size may be such that the parity check program 22 is stored in a plurality of blocks. However, the present invention is not limited to this. For example, a minimum unit of address designation, for example, one row in FIG.
[0039]
Next, the parity check operation according to the embodiment of the present invention will be described with reference to FIG. Prior to the parity check, a program check start command is issued from the host microcomputer 1 to the DSP 2. Then, the block to be checked is instructed from the host microcomputer 1 to the DSP 2. For example, the host microcomputer 1 instructs the head address in the RAM 20 of the block to be checked. In the DSP 2, a block to be checked is confirmed based on this instruction. When the block is confirmed, the parity check program 22 stored in the RAM 20 is executed, and the parity check for the designated block is executed.
[0040]
The parity check can be performed by various methods. For example, it is conceivable to perform a parity check using simple parity such as even parity or odd parity. A simple parity calculation is performed by the parity check program 22, and a value obtained by integrating the calculation results for each block is output. However, the present invention is not limited to this, and the parity check can be performed using XOR (Exclusive OR). XOR is obtained for the block data using a predetermined bit string prepared in advance. The check by XOR has an advantage that processing can be performed at higher speed. Also, CRC (cyclic redundancy check) can be used as a parity check method.
[0041]
As an example, the parity check of the fourth block of the DSP program 23 is performed by the parity check program 22. First, the parity calculation of the fourth block of the DSP program 23 is performed by the parity check program 22, and a parity calculation result 41 is obtained. Subsequently, the parity code 40 corresponding to the parity calculation result of the fourth block of the DSP program 23, which is a parity check target, is extracted from the RAM 20. The extracted parity code 40 and the parity calculation result 41 are compared by the comparison process 42.
[0042]
If, as a result of the comparison of the parity code 40 and the parity calculation result 41 by the comparison process 42, it is determined that both indicate the same value, the decision process 43 determines that the four blocks of the DSP program 23 on the RAM 20 It is determined that there is no error in the eyes, and a correct fixed value 44 indicating that fact is set in the register 46. For example, a predetermined area in the buffer area 24 of the RAM 20 can be used as the register 46.
[0043]
On the other hand, if it is determined that the parity code 40 and the parity calculation result 41 are different from each other as a result of the comparison process 42, an error is detected in the parity code 40 and / or the parity calculation result 41 by the determination process 43. The parity calculation result 41 by the parity check program 22 is set in the register 46.
[0044]
In other words, the correct answer is fixed in the register 46 if it is determined that there is no error in the block to be subjected to parity check (in this example, the fourth block of the DSP program 23) based on the parity calculation result 41 of the parity check program 22. If the value 44 is set and it is determined that there is an error, the operation result 41 itself of the parity operation determined to have an error is set in the register 46.
[0045]
When the parity check for one block of the DSP program 23 is completed, the parity check for the parity check program 22 stored in the RAM 20 is performed next. Parity calculation is performed by the parity check program 22 on the block in which the parity check program 22 is stored (in this example, blocks having addresses “0x0300” to “0x03FF”), and a parity calculation result 31 is obtained. Subsequently, the parity code 30 corresponding to the parity operation result of the parity check program 22 is extracted from the parity code 21 from the RAM 20. The extracted parity code 30 and the parity calculation result 31 are compared by a comparison process 32.
[0046]
If, as a result of the comparison between the parity code 30 and the parity calculation result 31 by the comparison process 32, they indicate the same value, it is determined by the determination process 33 that the parity check program 22 on the RAM 20 has no error. The correct fixed value 34 indicating that is determined and set in the register 36. For example, an area different from the area used as the register 46 in the buffer area 24 of the RAM 20 is used as the register 36.
[0047]
On the other hand, as a result of the comparison of the parity code 30 and the parity calculation result 31 by the comparison process 32, if both values are different from each other, an error is detected in the parity code 30 and / or the parity calculation result 31 by the determination process 43. The parity calculation result 31 by the parity check program 22 is set in the register 36.
[0048]
That is, in the same way as in the register 46 described above, the register 36 corrects if it is determined that there is no error in the parity check program 22 on the RAM 20 to be subjected to the parity check based on the parity calculation result 31 of the parity check program 22. If the fixed value 34 is set and it is determined that there is an error, the parity operation result 31 itself of the parity operation that is determined to have an error is set.
[0049]
Thus, when the parity check processing for one block of the fourth block of the DSP program 23 and the parity check program 22 itself is completed, the address in the RAM 20 of the block on which the parity check has been performed is sent from the DSP 2 to the host microcomputer 1. Be notified.
[0050]
When the host microcomputer 1 receives the address of the block subjected to the parity check notified from the DSP 2, the data set in the registers 36 and 46 in the RAM 20 of the DSP 2 is taken in by the host microcomputer 1. Then, based on the fetched data in the registers 36 and 46, a determination process is performed as to whether or not the data uploaded to the RAM 20 needs to be corrected. If it is determined that data correction is necessary, the data is re-uploaded to the RAM 20 and the data stored in the RAM 20 is corrected.
[0051]
As the correct fixed values 34 and 44, predetermined values that do not overlap with the result of the parity calculation by the parity check program 22 are used.
[0052]
FIG. 4 is a flowchart showing an example of data correction processing based on the parity check result by the host microcomputer 1. In the first step S10, the address of the block subjected to the parity check transmitted from the DSP 2 is received by the host microcomputer 1. In the next step S11, the host microcomputer 1 takes in the parity check result for the parity check program 22 set in the register 36.
[0053]
In step S12, it is determined whether or not the parity check result fetched from the register 36 in step S11 is the correct fixed value 34. If it is determined that the value fetched from the register 36 is the correct fixed value 34, it is determined that there is no problem in the parity check program 22 and the parity code 21 stored in the RAM 20, and the processing is stepped. The process proceeds to S13.
[0054]
On the other hand, if it is determined in step S12 that the value fetched from the register 36 is not the correct fixed value 34, the process proceeds to step S16. In step S <b> 16, a parity code corresponding to the parity check result for the parity check program 22, that is, the parity check program 13 in the memory 11 is extracted from the parity code 14 in the memory 11 of the host microcomputer 1. In step S17, it is determined whether or not the retrieved parity code matches the value fetched from the register 36 in step S11.
[0055]
If it is determined that the two match, the parity check program 22 in the RAM 20 is correct, but the parity code 21 is considered incorrect. That is, even if the parity calculation result 31 for the parity check program 22 has a correct value, if the parity code 30 compared with the parity calculation result 31 in the comparison process 32 is an incorrect value, the parity calculation result 31 and the parity check result The code 30 does not match, and the correct fixed value 34 is not set in the register 36. At this time, the correct parity calculation result for the parity check program 22 is set in the register 36.
[0056]
In this case, the process proceeds to step S18, and the parity code corresponding to the parity operation result for the parity check program 22 (parity check program 13) is extracted from the parity code 14 stored in the memory 11 of the host microcomputer 1, and the DSP2 Sent to and re-uploaded. The re-uploaded parity code is written in the corresponding area of the RAM 20 as the parity code 30 described above. When the re-upload of the parity code is completed, the process proceeds to step S15.
[0057]
In the above description, when re-uploading the parity code, only the corresponding data is extracted from the parity code 14 stored in the memory 11 and transmitted to the DSP 2. However, this is not limited to this example. A block including the corresponding data among the parity codes 14 stored in the memory 11 may be transmitted from the host microcomputer 1 to the DSP 2. Further, all the parity codes 14 stored in the memory 11 can be transmitted to the DSP 2.
[0058]
In step S15, a check process for the next block is prepared. That is, the host microcomputer 1 notifies the DSP 2 of the address of the block to be checked next. For example, in this example, the address of the fifth block of the DSP program 23 in the RAM 20 and the address of the parity check program 22 are notified to the DSP 2.
[0059]
When the address is notified, the parity calculation is performed on the block of the notified address in the RAM 20 in the DSP 2 as described above, and the correct fixed values 34 and 44 and the parity are stored in the registers 36 and 46 based on the parity calculation result. The calculation result is set. In the host microcomputer 1, the process proceeds to step S10, and a check process based on the values set in the registers 36 and 46 is performed.
[0060]
In the embodiment of the present invention, as described above, the DSP program 23 and the parity check program 22 stored in the RAM are alternately checked in units of blocks. Thus, the DSP program 23 can be checked while the parity check program 22 is always kept in a normal state, and the reliability of the check result is improved.
[0061]
On the other hand, if it is determined in step S17 described above that the two do not match, it is determined that the parity check program 22 on the RAM 20 is incorrect. In this case, the parity code 30 may be erroneous together with the parity check program 22 on the RAM 20. Therefore, the process proceeds to step S19, and the parity check program 13 stored in the memory 11 of the host microcomputer 1 is re-uploaded to the DSP 2. The re-uploaded parity check program 13 is stored in the RAM 20 as a parity check program 22. When the re-upload of the parity check program is completed, the process proceeds to step S15.
[0062]
The parity check process for the parity check program 22 is alternately executed for each block with respect to the parity check process performed for the DSP program 23. Therefore, after re-uploading the parity check program 22 in the above-described step S19, the same check process is performed again on the re-uploaded check program 22. At that time, it can be determined whether or not there is an error in the parity code 30 in the determination in step S17.
[0063]
As described above, if it is determined in step S12 that the value fetched from the register 36 is the correct fixed value 34, the parity check program 22 on the RAM 20 is assumed to have no error, and the process proceeds to step S13. Then, correction processing in block units is performed on the DSP program 23 in the RAM 20.
[0064]
In step S13, the host microcomputer 1 takes in the parity check result for the block (referred to as the fourth block of the DSP program) that is set in the register 46 and is to be checked by the DSP program 23. In the next step S14, it is determined whether or not the parity check result fetched from the register 46 in step S13 is the correct answer fixed value 44. If it is determined that the check result fetched from the register 46 is the correct fixed value 44, it is determined that there is no problem in the fourth block of the DSP program 23 stored in the RAM 20, and the process The process proceeds to S15.
[0065]
On the other hand, if it is determined in step S14 that the value fetched from the register 46 is not the correct fixed value 44, the process proceeds to step S20. In step S20, the parity code for the corresponding block in the DSP program 23 in the memory 11 is extracted from the parity code 14 in the memory 11 of the host microcomputer 1, that is, the fourth block of the DSP program 23 that is the target of the parity operation. In step S21, it is determined whether or not the extracted parity code matches the value fetched from the register 46 in step S13.
[0066]
If it is determined that they match, the fourth block of the DSP program 23 in the RAM 20 is correct, but the parity code 21 is incorrect, as in the case of the determination for the parity check program 22 described above. It is thought that there is. In this case, the process proceeds to step S22, and the parity code corresponding to the parity calculation result for the fourth block of the DSP program 23 is extracted from the parity codes stored in the memory 11 of the host microcomputer 1, and re-uploaded to the DSP 2. The The re-uploaded parity code is written in the corresponding area of the RAM 20 as the parity code 40 described above. When the re-upload of the parity code is completed, the process proceeds to step S15.
[0067]
On the other hand, if it is determined in step S21 that the two do not match, it is determined that the fourth block of the DSP program 23 that is the parity check target is incorrect. Therefore, the process proceeds to step S23, and the block corresponding to the fourth block of the DSP program 23 in the DSP program 12 stored in the memory 11 of the host microcomputer 1 is re-uploaded to the DSP 2. This re-uploaded block is written to the corresponding location in RAM 20. At this time, when the upload process is completed, the process proceeds to step S15.
[0068]
The memory check according to the embodiment of the present invention described with reference to FIGS. 3 and 4 can be performed when the DSP 2 is activated. For example, a series of memory check processing is performed after the host microcomputer 1 instructs the DSP 2 to start processing until the processing in the DSP 2 is actually started. The present invention is not limited to this, and the memory check process can also be executed when the DSP2 original process is not performed while the DSP2 is in operation. Further, the memory check process may be performed at any time when it can be executed while the DSP 2 is operating, or may be performed only once when the DSP 2 is activated. Further, if there is a margin in the processing capacity of the DSP 2, the memory check process may always be performed as a background to the original process during the operation of the DSP 2.
[0069]
Furthermore, it is not necessary to check all blocks of the RAM 20 in a series of memory check operations. For example, the processing can be temporarily interrupted when a check is performed up to a block in the middle of the RAM 20, and the check processing can be resumed from the block where the processing is interrupted when the check can be performed again.
[0070]
In the above description, it has been described that the memory check according to the embodiment of the present invention is performed by the host microcomputer 1 and the DSP 2. However, this is not limited to this example, and the essential part of the present invention is realized only on the DSP 2 side. Is possible. For example, in FIG. 4 described above, the data re-upload process, that is, the process excluding the processes of steps S18, S19, S22, and S23, can be executed only by the DSP2. Re-uploading of the parity code, parity check program, and DSP program can be performed by issuing a re-upload request from the DSP to the host microcomputer. In addition, by storing a plurality of the same parity codes in the DSP RAM, the parity operation result by the parity check program in steps S16 and S17 and steps S20 and S21 in FIG. 4 is compared with the correct parity code. It is possible to substitute the processing to do.
[0071]
【The invention's effect】
As described above, according to the present invention, since the parity check for the DSP RAM is performed for each block of a predetermined size, the number of times of communication between the DSP and the host microcomputer is reduced, so that the check time can be shortened. effective.
[0072]
Further, for the DSP program and the parity check program uploaded to the DSP RAM, the parity check for the parity check program stored in the RAM is performed by the uploaded parity check program. At this time, it is assumed that there is no error in the parity check program itself. Therefore, it is necessary to check the parity check program itself before performing the parity check of the DSP program.
[0073]
In the embodiment of the present invention, the parity check is performed in units of blocks and the parity check program is stored in one block, so that the check of the parity check program itself can be completed by one parity check process. Accordingly, the parity check of the DSP program and the parity check of the parity check program itself are alternately performed in units of blocks, so that it is possible to always confirm whether or not the parity check program itself is normal.
[0074]
In addition, since two parity check results, that is, a parity check result for the DSP program and a parity check result for the parity check program itself can be confirmed, it is instantaneous whether the DSP program has an error or the parity check program itself has an error. There is an effect that can be judged.
[0075]
Furthermore, in the embodiment of the present invention, when the parity check program itself is erroneous as a result of the parity check, the parity code by the parity check is output as it is. The data can be checked again using data stored in the memory. For this reason, it is possible to determine whether there is an error in the program to be checked or whether there is an error in the parity code that is compared with the parity operation result in the check.
[Brief description of the drawings]
FIG. 1 is a schematic diagram schematically showing a configuration of an example of a DSP system applicable to an embodiment of the present invention.
FIG. 2 is a schematic diagram showing an example data arrangement in a RAM in a DSP.
FIG. 3 is a diagram for explaining an operation of parity check according to an embodiment of the present invention.
FIG. 4 is a flowchart illustrating an example of data correction processing based on a parity check result by a host microcomputer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Host microcomputer, 2 ... DSP, 11 ... Memory, 12 ... DSP program, 13 ... Parity check program, 14 ... Parity code, 20 ... RAM, 21 ... Parity code, 22 ... Parity check program, 23 ... DSP program, 24 ... Buffer area, 30, 40 ... Parity code, 31, 41 ... Parity calculation result, 34, 44 ...・ Fixed correct value, 36, 46 ... Register

Claims (18)

In a memory check system that has a rewritable memory and checks the contents of a rewritable memory of a signal processing device configured to perform signal processing according to the contents written in the rewritable memory,
An execution program; a parity check program; and a host device having a memory in which the execution program and the parity code resulting from performing a parity operation on the parity check program are stored.
The execution device stored in the rewritable memory, connected to the host device and having a rewritable memory for storing the execution program, the parity check program and the parity code supplied from the host device A signal processing device for performing signal processing based on a program,
In the signal processing device, a unit of the rewritable memory with respect to the execution program and the parity check program stored in the rewritable memory by the parity check program stored in the rewritable memory. A memory check system, wherein a parity operation is performed for each block having a plurality of addresses and a detection code is output based on the result of the parity operation. The memory check system according to claim 1,
The memory check system, wherein the parity check program is stored in one or a plurality of the blocks in the rewritable memory. The memory check system according to claim 1,
The parity check program outputs a predetermined fixed value as the detection code if the result of the parity calculation indicates normal, and outputs the parity calculation as the detection code if the result of the parity calculation indicates abnormality. A memory check system characterized by outputting a result. The memory check system according to claim 1,
The memory check system, wherein the parity check program alternately performs the parity operation for the execution program and the parity operation for the parity check program in units of blocks. The memory check system according to claim 4,
The detection code based on the result of the parity operation for the execution program by the parity check program and the detection code based on the result of the parity operation for the parity check program are output to the host device. A memory check system characterized by that. The memory check system according to claim 1,
The memory check system further comprising the host device for checking the execution program, the parity check program and the parity code stored in the rewritable memory based on the detection code. . An execution program, a parity check program, and a host device having a memory for storing a parity code as a result of performing a parity operation on the execution program and the parity check program by the parity check program are connected to the host device. A rewritable memory of a signal processing apparatus having a rewritable memory for storing a supplied execution program, a parity check program, and a parity code, and performing signal processing based on the execution program stored in the rewritable memory In the memory check method for checking the contents of
A host device having a memory in which a signal processing device stores an execution program, a parity check program, an execution program by the parity check program, and a parity code obtained by performing a parity operation on the parity check program The execution program and the parity stored in the rewritable memory by the execution program, the parity check program, and the parity check program stored in the rewritable memory for storing the parity code. For the check program, a parity calculation step for performing a parity calculation for each block of a plurality of sizes of unit addresses of the rewritable memory,
Memory check how the signal processing unit, characterized in that a step of detecting code output for outputting a detection code based on the parity calculation result of the above steps parity operation. In a signal processing apparatus having a rewritable memory and configured to perform signal processing according to the contents written in the rewritable memory,
A rewritable memory for storing an execution program, a parity check program, and the execution program and a parity code obtained by performing a parity operation in advance on the parity check program in the parity check program;
Signal processing means for performing signal processing based on the execution program stored in the rewritable memory,
When the signal processing device uses the parity check program stored in the rewritable memory, the execution program stored in the rewritable memory and the unit address of the rewritable memory for the parity check program A signal processing apparatus, wherein a parity calculation is performed for each block having a plurality of sizes and a detection code based on the result of the parity calculation is output. The signal processing device according to claim 8,
The signal processing apparatus, wherein the parity check program is stored in one or a plurality of the blocks in the rewritable memory. The signal processing device according to claim 8,
The parity check program outputs a predetermined fixed value as the detection code if the result of the parity calculation indicates normal, and outputs the parity calculation as the detection code if the result of the parity calculation indicates abnormality. A signal processing apparatus characterized by outputting a result. The signal processing device according to claim 8,
The signal processing apparatus, wherein the parity check program alternately performs the parity operation for the execution program and the parity operation for the parity check program in units of blocks. The signal processing apparatus according to claim 11,
The detection code based on the result of the parity operation for the execution program by the parity check program and the detection code based on the result of the parity operation for the parity check program are transmitted to the rewritable memory. A signal processing apparatus, characterized in that the signal is output to an execution program, the parity check program, and a host device that supplies the parity code. In a memory check method of a signal processing apparatus having a rewritable memory and configured to perform signal processing according to the contents written in the rewritable memory,
A rewritable memory in which a signal processor stores an execution program, a parity check program, an execution program by the parity check program, and a parity code resulting from performing a parity operation on the parity check program in advance The parity check program stored in the rewritable memory is compared with the execution program stored in the rewritable memory and the parity check program for each block having a size of a plurality of unit addresses of the rewritable memory. A parity operation step to perform the operation;
A signal processing apparatus comprising: a detection code output step for outputting a detection code based on a result of the parity calculation in the parity calculation step. In a memory check program that has a rewritable memory and performs a memory check on a rewritable memory of a signal processing device configured to perform signal processing according to the contents written in the rewritable memory,
The signal processing device can rewrite the execution program, the memory check program for checking the memory by parity calculation, and the parity code resulting from performing the parity calculation on the execution program and the memory check program in advance. Parity calculation step of performing parity calculation for each block of a plurality of sizes of unit addresses of the rewritable memory for the execution program and the memory check program stored in the rewritable memory When,
Signal processing device, a memory check program, characterized in that it comprises the steps of detecting code output for outputting a detection code based on the result of the parity calculation by step of the parity calculation. The memory check program according to claim 14,
A memory check program stored in one or more of the blocks in the rewritable memory. The memory check program according to claim 14,
If the result of the parity operation indicates normal, a predetermined fixed value is output as the detection code. If the result of the parity operation indicates abnormality, the result of the parity operation is output as the detection code. A memory check program characterized by that. The memory check program according to claim 14,
A memory in which the parity operation for the execution program on the rewritable memory and the parity operation for the memory check program on the rewritable memory are alternately performed in units of blocks. Check program. The memory check program according to claim 17,
The detection code based on the result of the parity operation for the execution program on the rewritable memory, and the detection code based on the result of the parity operation for the memory check program on the rewritable memory, A memory check program, wherein the execution program, the parity check program, and the host device that supplies the parity code are output to a rewritable memory.

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