JP2004038541A - Memory check system, memory check method, signal processor, memory check method of signal processor, and memory check program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To precisely check a program or coefficient data on a RAM at high speed. <P>SOLUTION: A program 22 stored in a block having a prescribed size checks a DSP program 23 for every block, compares an operation result 41 with a corresponding parity code 40, and sets a fixed value 44, when the both are matched, or the operation result 41, when the both are not matched, to a register 46. The program 22 on the RAM 20 is similarly checked in the block unit, and sets a fixed value 34, when an operation result 31 is matched to a corresponding parity code 30, or the operation result 31, when the both are not matched, to a register 36. A host determines the validity of the parity code 21 and the programs 22 and 23 on the RAM 20 based on the values of the registers 36 and 46. The host supplies right data to a DSP 2 based on the determination result to correct the content of the RAM 20. The program 22 and the program 23 are alternately checked for each block, and the validity is regularly kept. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory check system, a memory check device and a method for checking data and a program stored in a memory, and a memory check program.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, for performing signal processing using a digital filter, for example, a DSP (Digital Signal Processor) has been widely used. The DSP constitutes an arithmetic unit that performs addition, subtraction, multiplication and division based on a program (instruction) and coefficient data stored in a ROM (Read Only Memory) or a RAM (Random Access Memory), and performs signal processing on an input digital signal. Is to do. In particular, a type of DSP that stores programs and coefficient data in a RAM can flexibly change the function of the DSP by rewriting the storage contents of the RAM. In such a DSP, for example, instruction data and coefficient data are generally downloaded from a microcomputer or the like that controls the DSP and stored in a RAM.
[0003]
The DSP has an instruction RAM for storing program codes and a coefficient RAM for storing coefficient data, and these are connected by a bus. The RAM is an instruction RAM and a coefficient RAM, and the coefficient RAM is, for example, a RAM for storing X coefficient data and a RAM for storing Y coefficient data, each of which is physically independent, and a bus connected to each RAM. Each has a physically independent configuration.
[0004]
This allows the DSP to read and write data from and to each RAM in parallel. For example, the DSP reads the X and Y coefficients from the RAM, performs arithmetic processing, and temporarily stores the arithmetic result in the RAM. A series of processes can be executed by one command. On the other hand, in a configuration using a CPU (Central Processing Unit), it is general that the CPU and the RAM are connected by a single bus, and in order to perform the above-described processing, each coefficient data is read, arithmetic processing, A plurality of commands are required according to each processing such as storing the result of the arithmetic processing in the RAM. Therefore, the DSP can operate at higher speed for processing centering on the product-sum operation than the CPU.
[0005]
Data stored in the RAM may be partially destroyed by the influence of static electricity or noise. In addition, if an error occurs during the writing, such as when the timing of writing data to the RAM does not match, incorrect data will be stored. Further, there is a possibility that the program itself has a bug and the RAM area is destroyed during the execution of the program. In the case where a DSP program and coefficient data are stored in the RAM and the DSP is used, if there is an error in the contents stored in the RAM, the DSP may not operate as expected, or the DSP may run away.
[0006]
[Problems to be solved by the invention]
Therefore, conventionally, several methods have been considered for detecting a runaway of the DSP and checking the contents stored in the RAM. As an example, a watchdog timer that detects an abnormal loop or runaway of a program by resetting a program counter every certain fixed period is known. According to this, for example, when the program counter indicating the execution position of the program is abnormal, this can be detected.
[0007]
As another example, in Japanese Patent Application Laid-Open No. Hei 5-313908, a program abnormality detection program for detecting an abnormality of an execution program is stored in an external memory in advance, and the program abnormality detection program is used. A method for detecting an error on a RAM is disclosed. The program for detecting a program abnormality is downloaded from the external memory to the RAM together with the program for execution. The presence / absence of the execution program and the program abnormality detection program in the RAM is checked by the program abnormality detection program, and the execution program and the program abnormality detection program in which the abnormality is detected are corrected.
[0008]
The program for detecting a program abnormality, for example, obtains a checksum or XOR for the program data or coefficient data stored in the RAM, and compares the obtained value with a check code such as a correct checksum value or XOR result prepared in advance. By comparing, programs and data are inspected.
[0009]
However, according to this method, an access is made in units of an address of the RAM, the data stored in the RAM is read, and then the read data is transferred to an error detection program or error detection means to detect an error. Therefore, if a large amount of data or program code can be easily processed with the improvement of the processing capability of the CPU or the DSP, the amount of RAM that must be checked increases, and much time is spent on the check time. There was a problem that it had to be done.
[0010]
In this method, a program abnormality detection program and a check code for detecting a program abnormality, and an execution program and coefficient data to be detected exist on the same RAM. Therefore, there is a problem that the program for detecting a program abnormality and the check code stored in the RAM, and the execution program and the coefficient data together therewith may be destroyed due to the influence of static electricity or the like.
[0011]
As still another example, Japanese Patent Application Laid-Open No. 2000-339230 discloses that information stored in a RAM is directly transferred to an error detection unit using DMA (Direct Memory Access), and an error is detected in the content stored in the RAM. A method for determining whether or not is included is disclosed. According to this method, not only program data stored in the RAM but also error detection of coefficient data and the like stored in the RAM can be detected. Therefore, it is possible to detect a data error such that the DSP or CPU operating based on the data stored in the RAM does not run out of control.
[0012]
Further, according to the method disclosed in Japanese Patent Laid-Open No. 2000-339230, it is not necessary to execute a detection program on the CPU when detecting an error in the program data or coefficient data stored in the RAM. There is an advantage that it is not necessary to overestimate the processing capacity of the CPU in consideration of data error detection. Further, since the error detecting means is provided separately from the RAM, even if the contents of the RAM are destroyed, the error detection itself can be performed without any problem.
[0013]
However, this method also has a problem that the check time increases as the RAM capacity increases, as described above.
[0014]
Therefore, an object of the present invention is to provide a memory check system, a memory check device and a method, and a memory check program that can check and correct program data and coefficient data stored in a RAM at high speed and accurately. It is in.
[0015]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the present invention provides a rewritable memory of a signal processing device having a rewritable memory and performing signal processing according to contents written in the rewritable memory. In a memory check system for checking contents, a memory for storing an execution program, a parity check program, and a parity code resulting from performing a parity operation on the execution program and the parity check program by the parity check program is provided. A host device, having a rewritable memory connected to the host device and storing an execution program, a parity check program, and a parity code supplied from the host device, based on the execution program stored in the rewritable memory; Signal for signal processing A signal processing device, wherein a parity check program stored in a rewritable memory is used to execute an execution program and a parity check program stored in the rewritable memory. A parity check is performed for each block of a plurality of sizes, and a detection code based on the result of the parity calculation is output.
[0016]
The present invention also provides a host device having a memory for storing an execution program, a parity check program, and a parity code obtained by performing a parity operation on the execution program and the parity check program in the parity check program. A signal processing device that is connected and has a rewritable memory for storing an execution program, a parity check program, and a parity code supplied from a host device, and performs signal processing based on the execution program stored in the rewritable memory In a memory check method for checking the contents of a rewritable memory, an execution program, a parity check program, and a parity operation for the execution program and the parity check program in the parity check program. A memory rewritable by an execution program, a parity check program, and a parity check program stored in a rewritable memory for storing a parity code, which are supplied from a host device having a memory for storing a parity code obtained as a result. Of a parity operation for performing a parity operation for each block having a plurality of unit addresses of a rewritable memory with respect to the execution program and the parity check program stored in the memory, and a result of the parity operation by the parity operation step And a detection code output step of outputting a detection code based on the memory check method.
[0017]
According to another aspect of the present invention, there is provided a signal processing apparatus having a rewritable memory and performing signal processing in accordance with the content written in the rewritable memory. A rewritable memory in which a parity code obtained by performing a parity operation on the execution program and the parity check program in advance by the check program is stored, and signal processing is performed based on the execution program stored in the rewritable memory. And a parity check program stored in the rewritable memory, for executing the execution program and the parity check program stored in the rewritable memory from a plurality of unit addresses of the rewritable memory. Size block Parity operation was carried out, a signal processing apparatus is characterized in that so as to output a detection code based on the result of the parity operation for each.
[0018]
The present invention also relates to a memory check method of a signal processing device having a rewritable memory and performing signal processing in accordance with the content written in the rewritable memory, comprising: an execution program; A parity check program stored in a rewritable memory in which a program and a parity code obtained by performing a parity operation on the execution program and the parity check program in advance by the parity check program are stored in a rewritable memory. A parity calculation step of performing a parity calculation for each of the blocks having a plurality of unit addresses of the rewritable memory with respect to the stored execution program and parity check program, and a result of the parity calculation by the parity calculation step A memory checking method of a signal processing device and having a detection code output step of outputting a detection codes based.
[0019]
Further, the present invention provides a memory check for executing a memory check on a rewritable memory of a signal processing device having a rewritable memory and performing signal processing according to contents written in the rewritable memory. In the program, an execution program, a memory check program for checking a memory by a parity operation, and a parity code obtained by performing a parity operation on the execution program and the memory check program in advance are stored in a rewritable memory, A parity calculation step of performing a parity calculation for each block of a plurality of unit addresses of the rewritable memory with respect to the execution program and the memory check program on the rewritable memory; A memory check program; and a detection code output step of outputting a detection code based on the result of the operation.
[0020]
As described above, the invention according to claims 1 and 7 provides an execution program, a parity check program, and a parity code obtained by performing a parity operation on the execution program and the parity check program in the parity check program. And a rewritable memory connected to the host device and storing an execution program, a parity check program, and a parity code supplied from the host device, and stored in the rewritable memory. A signal processing device that performs signal processing based on the executed program, wherein the signal processing device uses the parity check program stored in the rewritable memory to execute the execution program and the parity check stored in the rewritable memory. Program In contrast, the parity calculation is performed for each block of a plurality of rewritable memory unit addresses, and a detection code is output based on the result of the parity calculation. At the same time, the check of the execution program and the check of the parity check program itself can be performed alternately.
[0021]
According to the eighth and thirteenth aspects of the present invention, an execution program, a parity check program, and a parity code obtained by performing a parity operation on the execution program and the parity check program by the parity check program in advance are stored. A rewritable memory, and signal processing means for performing signal processing based on an execution program stored in the rewritable memory. The stored execution program and the parity check program are subjected to a parity operation for each block having a plurality of sizes of rewritable memory unit addresses, and a detection code based on the result of the parity operation is output. Because the memory With the time required for Ekku is shortened, it is possible to perform the checking check and parity check program itself of the execution program alternately.
[0022]
A memory check program according to a fourteenth aspect of the present invention includes an execution program, a memory check program for checking a memory by a parity operation, and a result of performing a parity operation on the execution program and the memory check program in advance. A parity code is stored in a rewritable memory, and a parity operation is performed on the execution program and the memory check program on the rewritable memory for each block of a plurality of sizes of unit addresses of the rewritable memory. Since it has an operation step and a detection code output step of outputting a detection code based on the result of the parity operation in the parity operation step, the time required for memory check is reduced, and the execution program check and self- Own and check can be performed alternately.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described. According to the present invention, an execution program and coefficient data used in a DSP (Digital Signal Processor) are downloaded from a memory of a microcomputer serving as a host (hereinafter, referred to as a host microcomputer) to a RAM (Random Access Memory) of the DSP, In a configuration in which the DSP is stored in the RAM of the DSP, a parity check program for checking the downloaded execution program and data stored in the RAM of the DSP by a parity operation is downloaded to the RAM of the DSP together with the DSP execution program and data. On the DSP side, the execution program and coefficient data stored in the RAM using the downloaded parity check program, and Check the program itself.
[0024]
At this time, according to the present invention, the execution program and the parity check program stored in the RAM are checked by the parity check program for each block having a plurality of sizes of the unit address of the RAM.
[0025]
Since the execution program, coefficient data, and parity check program are checked in units of blocks of a predetermined size, the time required for the check can be reduced. In addition, since the parity check program itself is also checked for each block, the execution program, coefficient data, and parity check program stored in the RAM can be alternately checked for each block. This makes it possible to always check whether the parity check program itself is normal or not.
[0026]
Further, according to the present invention, using the check program stored in the memory of the host microcomputer, the execution program and coefficient data downloaded to the DSP and stored in the RAM, and the check of the check program can be checked by a block of a predetermined size. It is done in units. Since the check is performed on both the DSP side and the host microcomputer side, it is possible to determine which of the check code used for the check and the check program is not normal.
[0027]
FIG. 1 schematically shows a configuration of an example of a DSP system applicable to an embodiment of the present invention. The host microcomputer 1 is, for example, a microcomputer having a CPU 10 and a memory 11 formed of a RAM and / or a ROM (Read Only Memory). The DSP 2 has a RAM 20, and operates based on an execution program and coefficient data stored in the RAM 20. The execution program of the DSP 2 is described by instruction codes that can be decoded by the DSP 2.
[0028]
The host microcomputer 1 and the DSP 2 are connected by an address bus 3 and a data bus 4. For example, a command for instructing the operation of the DSP 2 is transmitted from the host microcomputer 1 to the DSP 2 via the buses 3 and 4, and the DSP 2 is controlled by the host microcomputer 1.
[0029]
In the memory 11 of the host microcomputer 1, a DSP program 12, which is an execution program of the DSP 2, and coefficient data (not shown) are stored in advance. The DSP program stored in the memory 11 of the host microcomputer 1 is also described using the above-described instruction code. Hereinafter, the DSP program and the coefficient data used in the DSP program are collectively referred to as a DSP program.
[0030]
The DSP program is uploaded from the host microcomputer 1 to the DSP 2 and stored in the RAM 20 of the DSP 2. For example, an address of the RAM 20 is designated from the host microcomputer 1 to the DSP 2 via the address bus 3. The DSP program is uploaded from the host microcomputer 1 to the DSP 2 via the data bus 4. The uploaded DSP program is written to the RAM 20 based on the address specified using the address bus 3.
[0031]
The DSP 2 operates according to the DSP program downloaded from the host microcomputer 1. By changing the contents of the DSP program uploaded from the host microcomputer 1 to the DSP 2, the DSP 2 can perform different processing.
[0032]
Further, the memory 11 of the host microcomputer 1 includes a parity check program 13 for performing a parity check of the DSP program 12 uploaded to the DSP 2 and stored in the RAM 20, and a DSP program 12 and a parity check program 13 stored in the memory 11. And a parity code 14, which is a result of performing a parity operation in advance using the parity check program 13. The parity check program 13 is described by the above-described instruction code so as to be executable in the DSP 2. The parity check program 13 and the parity code 14 are uploaded from the host microcomputer 1 to the DSP 2 together with the above-mentioned DSP program 12, and stored in the RAM 20.
[0033]
FIG. 2 shows an example of a data arrangement in the RAM 20. In the example of FIG. 2, the RAM 20 has a capacity of 64 kB (kilobytes), and addresses are designated by “0x0000” to “0x10000”. In the address description, “0x” indicates that the description is in hexadecimal notation. The addresses “0x0400” to “0xAFFF” store the DSP program 23. The addresses “0xB000” to “0xFFFF” are the buffer area 24. The buffer area 24 is an area used when the DSP program 23 operates in the DSP 2, and its contents are changed as the DSP program is executed.
[0034]
The parity code 21 is stored in the addresses “0x0000” to “0x02FF”. The addresses “0x0300” to “0x03FF” store the parity check program 22. The parity code 21 is a parity code for data in all areas of the RAM 20 except the buffer area 24. That is, the parity code 21 corresponds to a result of performing a parity operation on the data in all the areas except the buffer area 24 of the RAM 20 using the parity check program 22 in advance. As described above, the parity of the buffer area 24 is not determined because the content is changed in accordance with the execution of the DSP program.
[0035]
Note that the capacity of the RAM 20 is not limited to 64 kB, and the address arrangement shown in FIG. 2 is also an example, and is not limited to this example.
[0036]
In the present invention, the parity check operation by the parity check program 22 is performed for each block in units of a block of a predetermined size. For example, one block is constituted by a size in which a plurality of unit addresses in the RAM 20 are aggregated. As an example, a block having a size corresponding to the area where the parity check program 22 is stored is defined as one unit block. In this example in which the capacity of the RAM 20 is 64 kB and the parity check program 22 has the address width “0x0100”, a block having a size of 256 bytes corresponding to the address width “0x0100” is defined as one unit block. Therefore, in the example of FIG. 2, the parity code 21 is composed of three blocks, and the DSP program 23 is composed of 172 blocks.
[0037]
The parity check operation by the parity check program 22 is performed for each block in units of one block having a size of 256 bytes. The parity code 21 calculated in advance and stored in the RAM 20 is also a parity code calculated by the DSP program 23 and the parity check program 22 in units of one block. By designating an address in the RAM 20 in a predetermined manner, a parity code corresponding to a parity operation in block units can be extracted from the parity code 21.
[0038]
In the above description, the size of the block has been described as being the same as the size of the parity check program 22, but this is not limited to this example. The size of the block can be arbitrarily set in units of address specification of the RAM 20. For example, the block size may be such that the parity check program 22 is stored in a plurality of blocks. However, the present invention is not limited to this. For example, a minimum unit of address specification, for example, one row in FIG. 2 can be a block.
[0039]
Next, the operation of the parity check according to the embodiment of the present invention will be described with reference to FIG. Prior to the parity check, a program check start command is issued from the host microcomputer 1 to the DSP 2. Then, a block to be checked is instructed from the host microcomputer 1 to the DSP 2. For example, the start address of the block to be checked in the RAM 20 is specified by the host microcomputer 1. In the DSP 2, a block to be checked based on this instruction is confirmed. When the block is confirmed, the parity check program 22 stored in the RAM 20 is executed, and the parity check for the designated block is executed.
[0040]
Note that the parity check can be performed by various methods. For example, it is conceivable to perform a parity check using simple parity such as even parity or odd parity. A simple parity calculation is performed by the parity check program 22, and a value obtained by integrating the calculation results for each block is output. The present invention is not limited to this, and the parity check can be performed using XOR (Exclusive OR). An XOR is obtained for the block data using a predetermined bit string prepared in advance. The check by XOR has an advantage that processing can be performed at higher speed. In addition, a CRC (cyclic redundancy check) may be used as a parity check method.
[0041]
As an example, the parity check of the fourth block of the DSP program 23 is performed by the parity check program 22. First, the parity calculation of the fourth block of the DSP program 23 is performed by the parity check program 22, and a parity calculation result 41 is obtained. Subsequently, the parity code 40 corresponding to the parity calculation result of the fourth block of the DSP program 23, which is a parity check target, is extracted from the RAM 20. The extracted parity code 40 and the parity operation result 41 are compared by a comparison process 42.
[0042]
If the result of the comparison between the parity code 40 and the parity operation result 41 by the comparison processing 42 is that they show the same value, the determination processing 43 determines that the four blocks of the DSP program 23 in the RAM 20 It is determined that there is no error in the eyes, and a correct answer fixed value 44 indicating this is set in the register 46. For example, a predetermined area in the buffer area 24 of the RAM 20 can be used as the register 46.
[0043]
On the other hand, as a result of the comparison between the parity code 40 and the parity operation result 41 by the comparison process 42, if both values are different, the judgment process 43 indicates that the parity code 40 and / or the parity operation result 41 have an error. It is determined that it exists, and the parity operation result 41 by the parity check program 22 is set in the register 46.
[0044]
That is, if it is determined in the register 46 based on the parity operation result 41 of the parity check program 22 that there is no error in the block to be parity-checked (the fourth block of the DSP program 23 in this example), the correct answer is fixed. The value 44 is set, and if it is determined that there is an error, the operation result 41 of the parity operation that is determined to have an error is set in the register 46 itself.
[0045]
When the parity check of one block of the DSP program 23 is completed, the parity check for the parity check program 22 stored in the RAM 20 is performed next. A parity operation is performed by the parity check program 22 on the block in which the parity check program 22 is stored (in this example, the blocks at addresses “0x0300” to “0x03FF”), and a parity operation result 31 is obtained. Subsequently, the parity code 30 corresponding to the parity operation result of the parity check program 22 is extracted from the RAM 20 among the parity codes 21. The extracted parity code 30 and the parity operation result 31 are compared by a comparison process 32.
[0046]
If the result of the comparison between the parity code 30 and the parity operation result 31 by the comparison process 32 indicates that the parity code 30 and the parity operation result 31 indicate the same value, it is determined that there is no error in the parity check program 22 on the RAM 20 by the determination process 33. The determination is made, and the correct answer fixed value 34 indicating that is set in the register 36. For example, an area of the buffer area 24 of the RAM 20 that is different from the area used as the register 46 is used as the register 36.
[0047]
On the other hand, as a result of the comparison between the parity code 30 and the parity operation result 31 by the comparison process 32, if both values are different, the judgment process 43 indicates that the parity code 30 and / or the parity operation result 31 have an error. It is determined that it exists, and the parity operation result 31 by the parity check program 22 is set in the register 36.
[0048]
That is, as in the case of the register 46 described above, the correct answer is obtained if it is determined that there is no error in the parity check program 22 on the RAM 20 to be subjected to the parity check based on the parity operation result 31 of the parity check program 22. When the fixed value 34 is set and it is determined that there is an error, the parity operation result 31 itself of the parity operation that is determined to have an error is set.
[0049]
When the parity check processing of the fourth block of the DSP program 23 and the parity check program 22 itself has been completed for one block, the DSP 2 sends the host microcomputer 1 the address of the parity-checked block in the RAM 20 for the host microcomputer 1. Notified.
[0050]
When the host microcomputer 1 receives the address of the block on which the parity check has been notified from the DSP 2, the data set in the registers 36 and 46 in the RAM 20 of the DSP 2 is taken in by the host microcomputer 1. Then, based on the fetched data of the registers 36 and 46, a process of determining whether or not the data uploaded to the RAM 20 needs to be corrected is performed. If it is determined that the data needs to be corrected, the data is re-uploaded to the RAM 20 and the data stored in the RAM 20 is corrected.
[0051]
As the correct answer fixed values 34 and 44, predetermined values that do not overlap with the result of the parity calculation by the parity check program 22 are used.
[0052]
FIG. 4 is a flowchart illustrating an example of a data correction process by the host microcomputer 1 based on a parity check result. In the first step S10, the host microcomputer 1 receives the address of the block on which parity check has been performed, transmitted from the DSP 2. In the next step S11, the host microcomputer 1 fetches the parity check result for the parity check program 22 set in the register 36.
[0053]
In step S12, it is determined whether or not the parity check result fetched from the register 36 in step S11 is the correct answer fixed value 34. If it is determined that the value fetched from the register 36 is the correct answer fixed value 34, it is determined that there is no problem in the parity check program 22 and the parity code 21 stored in the RAM 20, and the process proceeds to step The process moves to S13.
[0054]
On the other hand, if it is determined in step S12 that the value fetched from the register 36 is not the correct answer fixed value 34, the process proceeds to step S16. In step S16, the parity code corresponding to the parity check result of the parity check program 22, that is, the parity check program 13 in the memory 11, is extracted from the parity codes 14 in the memory 11 of the host microcomputer 1. Then, in step S17, it is determined whether or not the extracted parity code matches the value fetched from the register 36 in step S11 described above.
[0055]
If it is determined that they match, the parity check program 22 in the RAM 20 is correct, but the parity code 21 is considered to be incorrect. That is, even if the parity calculation result 31 for the parity check program 22 has a correct value, if the parity code 30 compared with the parity calculation result 31 in the comparison process 32 has an incorrect value, the parity calculation result 31 and the parity calculation result 31 The code 30 does not match, and the correct fixed value 34 is not set in the register 36. At this time, the correct parity operation result for the parity check program 22 is set in the register 36.
[0056]
In this case, the process proceeds to step S18, where the parity code corresponding to the parity operation result for the parity check program 22 (parity check program 13) is extracted from the parity codes 14 stored in the memory 11 of the host microcomputer 1, and the DSP 2 Sent to and re-uploaded. The re-uploaded parity code is written in the corresponding area of the RAM 20 as the parity code 30 described above. When the re-upload of the parity code is completed, the process proceeds to step S15.
[0057]
In the above description, when the parity code is re-uploaded, only the corresponding data from the parity code 14 stored in the memory 11 is extracted and transmitted to the DSP 2, but this is not limited to this example. The block including the corresponding data among the parity codes 14 stored in the memory 11 may be transmitted from the host microcomputer 1 to the DSP 2. Further, all the parity codes 14 stored in the memory 11 can be transmitted to the DSP 2.
[0058]
In step S15, a check process for the next block is prepared. That is, the host microcomputer 1 notifies the DSP 2 of the address of the next block to be checked. For example, in this example, the address of the fifth block of the DSP program 23 in the RAM 20 and the address of the parity check program 22 are notified to the DSP 2.
[0059]
When the address is notified, the DSP 2 performs the parity operation on the block of the notified address in the RAM 20 as described above, and stores the correct answer fixed values 34 and 44 and the parity in the registers 36 and 46 based on the parity operation result. The operation result is set. Then, in the host microcomputer 1, the process proceeds to step S10, and a check process based on the values set in the registers 36 and 46 is performed.
[0060]
In the embodiment of the present invention, the checks on the DSP program 23 and the parity check program 22 stored in the RAM are performed alternately in block units. Accordingly, the DSP program 23 can be checked while the parity check program 22 is always kept in a normal state, and the reliability of the check result is improved.
[0061]
On the other hand, if it is determined in step S17 that the two do not match, it is determined that the parity check program 22 in the RAM 20 is incorrect. In this case, there is a possibility that the parity code 30 as well as the parity check program 22 on the RAM 20 are incorrect. Then, the process proceeds to step S19, and the parity check program 13 stored in the memory 11 of the host microcomputer 1 is uploaded again to the DSP 2. The re-uploaded parity check program 13 is stored in the RAM 20 as the parity check program 22. When the re-upload of the parity check program is completed, the process moves to step S15.
[0062]
The parity check processing for the parity check program 22 is executed alternately for each block with respect to the parity check processing performed for the DSP program 23. Therefore, after re-uploading the parity check program 22 in the above-described step S19, a similar check process is executed again on the re-uploaded check program 22. At this time, it can be determined whether or not the parity code 30 has an error in the determination in step S17 described above.
[0063]
As described above, when it is determined in step S12 that the value fetched from the register 36 is the correct answer fixed value 34, it is determined that there is no error in the parity check program 22 in the RAM 20, and the process proceeds to step S13. Then, a correction process is performed on the DSP program 23 in the RAM 20 in block units.
[0064]
In step S13, the host microcomputer 1 fetches the parity check result of the block to be checked by the DSP program 23 (the fourth block of the DSP program) set in the register 46. In the next step S14, it is determined whether or not the parity check result fetched from the register 46 in step S13 is the correct answer fixed value 44. If it is determined that the check result fetched from the register 46 is the correct fixed value 44, it is determined that there is no problem in the fourth block of the DSP program 23 stored in the RAM 20, and The process moves to S15.
[0065]
On the other hand, if it is determined in step S14 that the value fetched from the register 46 is not the correct answer fixed value 44, the process proceeds to step S20. In step S20, of the parity code 14 in the memory 11 of the host microcomputer 1, the parity code for the fourth block of the DSP program 23, which is the target of the parity operation, that is, the corresponding block in the DSP program 12 in the memory 11 is extracted. Then, in step S21, it is determined whether or not the extracted parity code matches the value fetched from the register 46 in step S13.
[0066]
If it is determined that they match, the fourth block of the DSP program 23 in the RAM 20 is correct, but the parity code 21 is incorrect, as in the case of the above-described determination of the parity check program 22. It is thought that there is. In this case, the process proceeds to step S22, and the parity code corresponding to the parity operation result for the fourth block of the DSP program 23 is extracted from the parity codes stored in the memory 11 of the host microcomputer 1 and re-uploaded to the DSP 2. You. This re-uploaded parity code is written to the corresponding area of the RAM 20 as the parity code 40 described above. When the re-upload of the parity code is completed, the process proceeds to step S15.
[0067]
On the other hand, if it is determined in step S21 that the two do not match, it is determined that the fourth block of the DSP program 23 that is the parity check target is incorrect. Then, the process proceeds to step S23, and the block corresponding to the fourth block of the DSP program 23 in the DSP program 12 stored in the memory 11 of the host microcomputer 1 is re-uploaded to the DSP 2. This re-uploaded block is written to the corresponding location in RAM 20. At this time, when the upload processing is completed, the processing shifts to Step S15.
[0068]
The memory check according to the embodiment of the present invention described with reference to FIGS. 3 and 4 can be performed when the DSP 2 is started. For example, a series of memory check processes is performed from when the host microcomputer 1 instructs the DSP 2 to start processing to when the processing in the DSP 2 is actually started. However, the present invention is not limited to this, and the memory check process can be executed when the DSP2 original process is not performed while the DSP2 is operating. In addition, the memory check process may be performed at any time during the operation of the DSP 2 at an executable timing, or may be performed only once when the DSP 2 is started. Further, if the DSP 2 has sufficient processing capacity, the memory check processing may be performed at all times as a background for the original processing during the operation of the DSP 2.
[0069]
Furthermore, in a series of memory check operations, it is not necessary to check all blocks in the RAM 20. For example, the processing can be temporarily interrupted when a check is performed up to a block in the middle of the RAM 20, and when the check can be performed again, the check processing can be restarted from the block where the processing was interrupted.
[0070]
In the above description, the memory check according to the embodiment of the present invention has been described as being performed by the host microcomputer 1 and the DSP 2, but this is not limited to this example. It is possible. For example, in FIG. 4 described above, the data re-upload processing, that is, the processing excluding the processing of steps S18, S19, S22, and S23 can be executed only by the DSP 2. The re-upload of the parity code, the parity check program, and the DSP program can be performed by issuing a re-upload request from the DSP to the host microcomputer. Also, by storing a plurality of identical parity codes in the RAM of the DSP, the results of the parity calculation by the parity check program in steps S16 and S17 and steps S20 and S21 in FIG. 4 are compared with the correct parity code. Can be substituted.
[0071]
【The invention's effect】
As described above, according to the present invention, the parity check on the RAM of the DSP is performed for each block of a predetermined size, so that the number of times of communication between the DSP and the host microcomputer is reduced, so that the check time can be shortened. effective.
[0072]
In addition, for the DSP program and the parity check program uploaded to the RAM of the DSP, the parity check program uploaded performs a parity check on the parity check program stored in the RAM. At this time, it is assumed that there is no error in the parity check program itself. Therefore, it is necessary to check the parity check program itself before performing the parity check of the DSP program.
[0073]
In the embodiment of the present invention, the parity check is performed in units of blocks and the parity check program is contained in one block. Therefore, the parity check program itself can be completed by one parity check process. Therefore, by performing the parity check of the DSP program and the parity check of the parity check program itself alternately in block units, there is an effect that it is always possible to confirm whether the parity check program itself is normal or not.
[0074]
In addition, since the two parity check results, that is, the parity check result for the DSP program and the parity check result for the parity check program itself, can be confirmed, it is instantaneous whether there is an error in the DSP program or the parity check program itself. There is an effect that can be determined.
[0075]
Further, according to the embodiment of the present invention, when the parity check finds that the parity check program itself has an error, the parity code by the parity check is output as it is. The check can be performed again using the data stored in the memory. Therefore, it is possible to determine whether there is an error in the program to be checked or whether there is an error in the parity code that is compared with the parity operation result in the check.
[Brief description of the drawings]
FIG. 1 is a schematic diagram schematically showing a configuration of an example of a DSP system applicable to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an example of a data arrangement in a RAM in a DSP.
FIG. 3 is a diagram for explaining an operation of a parity check according to the embodiment of the present invention;
FIG. 4 is a flowchart illustrating an example of data correction processing by a host microcomputer based on a parity check result.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Host microcomputer, 2 ... DSP, 11 ... Memory, 12 ... DSP program, 13 ... Parity check program, 14 ... Parity code, 20 ... RAM, 21 ... Parity code, 22 Parity check program, 23 DSP program, 24 Buffer area, 30, 40 Parity code, 31, 41 Parity operation result, 34, 44 -Correct answer fixed value, 36, 46 ... register

Claims (18)

A memory check system that has a rewritable memory and checks the content of a rewritable memory of a signal processing device that is configured to perform signal processing according to the content written in the rewritable memory,
A host device having a memory for storing an execution program, a parity check program, and a parity code obtained by performing a parity operation on the execution program and the parity check program with the parity check program;
A rewritable memory connected to the host device and storing the execution program, the parity check program, and the parity code supplied from the host device, wherein the execution program stored in the rewritable memory is stored. A signal processing device that performs signal processing based on a program,
In the signal processing device, the parity check program stored in the rewritable memory allows the execution program and the parity check program stored in the rewritable memory to have a unit of the rewritable memory. A memory check system wherein a parity operation is performed for each block having a plurality of addresses and a detection code is output based on a result of the parity operation. The memory check system according to claim 1,
The memory check system, wherein the parity check program is stored in one or a plurality of the blocks in the rewritable memory. The memory check system according to claim 1,
The parity check program outputs a predetermined fixed value as the detection code if the result of the parity operation indicates normal, and outputs the predetermined code as the detection code if the result of the parity operation indicates abnormal. A memory check system characterized by outputting a result. The memory check system according to claim 1,
The memory check system, wherein the parity check program alternately performs the parity calculation for the execution program and the parity calculation for the parity check program in block units. The memory check system according to claim 4,
According to the parity check program, the detection code based on the result of the parity operation for the execution program and the detection code based on the result of the parity operation for the parity check program are output to the host device. A memory check system characterized by: The memory check system according to claim 1,
A memory check system, wherein the host device performs a check on the execution program, the parity check program, and the parity code stored in the rewritable memory based on the detection code. . An execution program, a parity check program, a parity check program, and a host device having a memory storing a parity code obtained by performing a parity operation on the execution program and the parity check program in the parity check program. A rewritable memory of a signal processing device having a rewritable memory for storing a supplied execution program, a parity check program, and a parity code, and performing signal processing based on the execution program stored in the rewritable memory In the memory check method for checking the contents of
The parity check program supplied from a host device having a memory for storing an execution program, a parity check program, and a parity code obtained by performing a parity operation on the execution program and the parity check program in the parity check program. The execution program, the parity check program, and the parity check program stored in the rewritable memory that stores the parity code are used to execute the parity check program and the execution program stored in the rewritable memory. A parity calculation step of performing a parity calculation for each block having a size of a plurality of unit addresses of the rewritable memory;
Outputting a detection code based on a result of the parity operation in the parity operation step. In a signal processing device having a rewritable memory and performing signal processing according to the content written in the rewritable memory,
A rewritable memory in which an execution program, a parity check program, and a parity code obtained by performing a parity operation on the execution program and the parity check program in advance with the parity check program are stored;
Signal processing means for performing signal processing based on the execution program stored in the rewritable memory,
The parity check program stored in the rewritable memory allows the execution program and the parity check program stored in the rewritable memory to have a plurality of unit addresses of the rewritable memory. A signal processing apparatus for performing a parity operation for each of the blocks and outputting a detection code based on a result of the parity operation. The signal processing device according to claim 8,
The signal processing device according to claim 1, wherein the parity check program is stored in one or a plurality of the blocks in the rewritable memory. The signal processing device according to claim 8,
The parity check program outputs a predetermined fixed value as the detection code if the result of the parity operation indicates normal, and outputs the predetermined code as the detection code if the result of the parity operation indicates abnormal. A signal processing device for outputting a result. The signal processing device according to claim 8,
The signal processing device according to claim 1, wherein the parity check program alternately performs the parity calculation for the execution program and the parity calculation for the parity check program in block units. The signal processing device according to claim 11,
By the parity check program, the detection code based on the result of the parity operation on the execution program, and the detection code based on the result of the parity operation on the parity check program, for the rewritable memory, A signal processing device for outputting to a host device that supplies an execution program, the parity check program, and the parity code. A memory check method of a signal processing device having a rewritable memory and performing signal processing in accordance with the content written in the rewritable memory,
The execution program, the parity check program, and the parity program which are stored in a rewritable memory in which an execution program and a parity code obtained by performing a parity operation on the parity check program in advance are stored. A parity operation for performing a parity operation on the execution program and the parity check program stored in the rewritable memory for each block having a plurality of unit addresses of the rewritable memory by a parity check program. Steps and
A detection code output step of outputting a detection code based on a result of the parity operation in the parity operation step. A memory check program that has a rewritable memory and executes a memory check on the rewritable memory of the signal processing device that is configured to perform signal processing according to the content written in the rewritable memory,
An execution program, a memory check program for checking a memory by a parity operation, and a parity code obtained by performing the parity operation on the execution program and the memory check program in advance are stored in a rewritable memory; A parity operation step of performing a parity operation on the execution program and the memory check program on the rewritable memory for each block having a plurality of unit addresses of the rewritable memory;
A detection code output step of outputting a detection code based on a result of the parity operation in the parity operation step. 15. The memory check program according to claim 14, wherein the memory check program is stored in one or a plurality of the blocks in the rewritable memory. 15. The memory check program according to claim 14, wherein a predetermined fixed value is output as the detection code if the result of the parity operation indicates normal, and the detection code is output if the result of the parity operation indicates abnormal. A memory check program for outputting a result of the parity operation. 15. The memory check program according to claim 14, wherein the parity calculation for the execution program on the rewritable memory and the parity calculation for the memory check program on the rewritable memory are alternately performed in block units. A memory check program characterized in that the program is executed in the following manner. 18. The memory check program according to claim 17, wherein the detection code based on a result of the parity calculation for the execution program on the rewritable memory, and the parity calculation for the memory check program on the rewritable memory. Wherein the detection code based on the result of the above is output to the host program which supplies the execution program, the parity check program, and the parity code to the rewritable memory. Check program.

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